Trip Report
2007 Design Automation Conference (DAC)
John Weiland, Intrinsix Corp.
The opinions expressed here represent those of the author, and not necessarily those of Intrinsix Corp. or
any other organization.
General
Attendance was moderate this year; good on Monday but pretty slow by Wednesday; about half the
giveaways at booths went to people staffing different booths. The official theme was automotive, but that
really wasn’t the dominant theme. The most common theme was low power, and it was sometimes overused,
like one company selling soft IP that they claimed was somehow “low power”. Cadence said a lot of their
customers are going directly from 130 nm to 65 nm, so that no doubt enhances the urgency of the low power
issues.
Cadence had threatened to pull out of DAC, but then reconsidered and had a booth this year. It was smallish
(smaller than the booths for Denali, Atrenta, Apache or Synplicity) but it was at an entrance and they did a
lot of giveaways, including a laptop every day and an X-box 360 every hour. They threw a very nice party
“for logic designers only” (and there really were no suits there). At DAC there was an undertone of “Cadence
is evil”. I attended one interoperability breakfast where that was a theme and there was even a small
“Cadence is evil” booth (the Interoperable P-Cell Library booth). Cadence uses their own format for power
files, and also has not allowed others to use P-cells for analog layout. Competitors are now seeking to define
standards (like UPF and Py-Cells) that they hope will pit Cadence against the rest of the world. Cadence’s
response for power formats (on numerous posters at DAC) is that their format is “Open – Inclusive – Real”.
Industry Overview
EDAC
Historically EDAC and Dataquest have jointly sponsored a presentation late afternoon on the Sunday
preceding the start of DAC. Dataquest did most of the presentations, and it was heavily attended by the Wall
Street types. Dataquest has gone the way of the dinosaur, so EDAC did it alone. Lacking impartial analysts
to fill the time, EDAC sponsored a panel discussion on the major issues in EDA right now.
Problems highlighted by the panel included the difficulty in creating novel architectures versus reusing the
same old things, the need for better power management tools, and the need to decrease the number of
degrees of freedom when doing initial system design and architecture so that the engineer does not have to
examine thousands of possibilities. One panelist bemoaned the fact that ESL (Electronic System Level) tools
are not being used as widely as they could be. One panelist thought a number of tools would be needed for
ESL, not just one. This agrees with a Gary Smith talk I heard years ago that stressed that ESL tools tend to
be specific to the application, unlike most EDA tools.
They also talked about IP reuse issues, specifically the difficulty with accurate revision control, handoff
issues, and problems integrating analog IP. One panelist complained that the darn analog IP users keep
insisting the IP be customized; this job would be easy if it weren’t for the customers. They noted that the
criteria for IP signoff vary with the IP so a standard flow is difficult.
For logic verification, one panelist suggested using system level verification metrics versus functional
coverage. Another bemoaned the fact that designers never trust the models they get so they build in slop
and never get the full benefit of the technology they are using. Personally, I have used at least 30 libraries in
my career and the next one I see without errors will be the first one ever. I have also created several libraries
of my own so I know the delay numbers have one digit accuracy (at best) because they depend on so many
assumptions. The good news is that fundamentally it’s a question of yield, so it’s all shades of gray and not
black and white.
Jim Solomon, one of the founders of Cadence, complained that SPICE simulators are too slow, analog
designers need more intelligent Monte Carlo simulations to cut down on the number of simulations, and they
also need better mixed signal simulators.
I didn’t understand some of the comments from the panel. Several panelists seemed to think that System
Verilog was the key to doing vendor-independent functional verification, in contrast to Specman from
Cadence or Vera from Synopsys. This seems a bit naïve to me. Unless you plan to do the entire
infrastructure yourself, you will want to use a pre-existing infrastructure like Synopsys VMM or Mentor AVM,
and once you start down that path the vendors have worked hard to insure that you can’t switch to a
competitor. They also discussed the problems of functional verification, and one panelist thought logic BIST
was the answer, in part because you already know the part is testable at tapeout, instead of postponing
ATPG until after tapeout and then finding out you should have modified the design to make it more testable.
Logic BIST is good for verifying that the silicon equals the netlist (or RTL?), but when most people talk about
functional verification they are talking about verifying that the RTL equals the fuzzy idea that was the genesis
of the specification. Logic BIST does not address that at all.
Gary Smith
Gary Smith, former head analyst of Dataquest, did his own bootleg presentation immediately following the
EDAC presentation (in the same hotel), and as always had the best food. Gary’s presentation concentrated
on multiprocessor issues.
Gary’s presentation also got into the interesting situation with fabs. He thinks about forty fabs will be closing
in 2007 and 2008, with much of the equipment going to mainland China or to MEMS manufacturers.
Other issues he highlighted were the need for better power prediction and for the ability to easily mix IP from
different vendors. He also said there is poor communication between chip designers and package and board
suppliers (there are lots of considerations with bond length and height, etc. that chip designers don’t think
about), and some of the package design software really doesn’t work.
In terms of who is really buying chips, he said that for fabless companies about 42% of the business is
communications, 34% consumer, 23% data processing, and 1% mil/aero.
Gary’s analyst emphasized the need for more work on designing multiprocessor systems, and bemoaned the
fact that (she claimed) few universities teach parallel programming any more. She said that much of the work
in multiprocessor systems is in homogenous systems, which are much easier to program than
heterogeneous systems. For heterogeneous systems, Gary said many of the existing tools are only good for
programming systems with exactly 2 processors. Gary then emphasized the need to USE multiprocessor
systems in addition to designing them. He emphasized the need for actual multithreading (different
processors doing different things) and said it would bring bigger gains than simple multiprocessing (different
processors doing the same thing). He said that many tools are now being written for multithreading, and it is
much harder than rewriting them for 64 bit operation. In know at Cadence’s 45 nm talk they said they were
working on multi-threading all their compute-intensive tools.
Keynote speeches
They had three keynote speeches again this year, since two are clearly not enough. The committee was
careful to prevent overlap, so one talk was on future uses of technology, one was on the details of current
technology challenges, and one was on some blue sky potential future technology. All are available at www.
dac.com.
Monday’s keynote was by Larry Burns, Vice President of R&D and Strategic Planning for GM. The official
theme for this DAC was automotive (the unofficial one was low power). His talk covered lots of exciting
developments he felt would occur in the automotive industry and centered on cars with electric power trains
powered by either batteries or hydrogen fuel cells. He noted that the number of cars is projected to almost
double in the next 15 years, which will cause many problems, including pollution and increasing dependence
on petroleum. He noted the new Chevy Sequel was recently driven 300 miles on public roads on a single
tank of hydrogen. He emphasized the idea of a single power train that could be customized with either lots of
batteries or hydrogen tanks or a combination of the two. He also talked about future technology
enhancements on his company’s products. He said On-Star will sense an accident because of airbag
deployment, get information on the forces in the accident, and notify emergency personnel if appropriate.
Vehicle to vehicle communications (V2V) could involve vehicles that are slow or stopped, vehicles doing
emergency braking, or vehicles that have been in an accident notifying other vehicles behind them. He
foresaw a steady progression from technology providing warnings to drivers, to semi-autonomous driving, to
on-demand autonomous driving, to fully autonomous driving.
On Tuesday Oh-Kyun Kwon, president of the System LSI Division for Samsung, presented his talk. He said
that the semiconductor business will continue to grow because of applications. He thought we were currently
in the age of consumer and mobile products driving the market, but in the future things like driverless cars,
biochips and robots might drive it. He listed a number of issues in the industry. The first was the huge capital
investments involved in creating a new fab. He thought that a new 12 inch fab costs about $2B to $3B and
when 18 inch fabs become available they will probably cost about $5B. This means that by his calculations
only 6 companies on earth have the revenues to buy a new fab. Another issue he foresaw was how to use all
the 8 inch fabs so that they don’t undercut prices for the 12 inch ones. He thought they should produce
items that don’t really benefit much from shrinking, like sensors, analog/RF parts, display drivers, etc. I
personally think economic forces will determine what they produce and telling them won’t matter much. He
thought that shrinking analog was extremely hard and the answer was going to SIP (system in package)
rather than SOC (system on chip); he thought SIP was cheaper and faster to design. He thought that at 65
nm a new design will cost about $46M (the majority in software development costs) and the demand for
ASSPs will continue to grow while ASICs shrink. He emphasized the value of a single design that could be
produced at several fabs, which of course makes sense since his company has such an arrangement with
IBM and Chartered. He thought that as feature sizes shrink, models must stop being continuous and start
taking the size of atoms into account. One challenge he presented was to provide a standard interface
between the fabs and design. My opinion is that part of this is the fault of the fabs. For fabs willing to provide
exact yield information to customers (in order to estimate yield of their design), each has decided to use a
different encrypted format. He also challenged the EDA industry to create better design cores for many-core
designs. He thought that as devices vary more at smaller feature sizes, the designs need the ability to adapt.
This could mean changing voltage (like adaptive voltages scaling), changing clock phase, etc. but generally
meant that the design would adapt to the peculiarities of the devices used to implement it.
On Thursday Jan Rabaey of UC Berkeley talked about synthetic biology. This is different from normal
biotechnology, where people are synthesizing new drugs or tweaking the DNA of something to include
certain traits. In synthetic biology, people use small, pre-characterized building blocks to implement higher
level functions. This methodology is fundamentally similar to IC design and many of the players providing
funding are semiconductor folks rather that biotech folks. He thought the fundamentals of IC design, like
abstracting away unnecessary details and using standard interfaces (SPICE netlist, GDSII, etc.) needed to
be carried into this field. He also thought that biology could teach IC designers a thing or two. For example,
one paper at DAC talked about using nanotubes for logic even if the manufacture was flawed. He noted that
crickets chirp in unison by listening to surrounding crickets, and thought this could be applied to clock
distribution on an IC. Instead of trying to distribute a clock to the entire chip, he foresaw many local clock
oscillators that synchronized with each other over time.
Cadence 45 nm talk
I attended a Cadence presentation on the challenges at 45 nm. They noted that some customers are
skipping 90 nm and going directly from 130 to 65, with 20% of design starts so far in 2007 being 65 nm. That
means 45 nm isn’t far off. They listed four challenges: productivity, low power, yield and mixed signal. At 45
nm, width and thickness of layers on the same chip can vary 10-40%, so OCV is a killer. They are pushing
clock meshes versus clock trees, as well as yield analysis. For gated clocks, they use a “hybrid mesh” where
the mesh is one level before the leaf cells and the gating cells drive the actual flops. Their tools also swap in
larger, slower, higher yielding cells in non-critical paths, insert double cut vias and does wire widening and
spreading.
Standards
In the realm of standard databases, a few years back Magma announced that their single combined
database, which is used “as is” by their tools, gave them a big advantage. Synopsys then announced that it
was combining the original Synopsys liberty (.lib) format with Avanti’s Milkyway database. They eventually
gave up and decided to use a single name to refer to both, implying they were somehow connected.
Cadence is known for buying random tools and trying to bolt them into a flow using various translators, which
is as far from a standard database as one can get. They were waiting until the OpenAccess standard was
defined by a committee, which was greatly delayed, leaving them last in the database wars. When it finally
was defined, various small companies decided to be compatible with it and Cadence bought most of them.
Interestingly Synopsys is now an advocate for OpenAccess. At a breakfast sponsored by Synopsys that I
attended, various vendors praised it. The National Semiconductor representative said that QA testing of a
new PDK is linear with the number of tools. One tool takes about 10 months. Wider use of OpenAccess
would mean easier and better QA. The representative from TSMC said that custom analog design needs
interoperability, meaning that you need interoperable P-Cells (the “Cadence is evil” theme). He also
complained about the effort involved in checking a PDK.
A number of vendors are trying to use Py-Cells from Ciranova as a standard in competition with Cadence’s P-
Cells.
A number of vendors are planning to use the Universal Power Format (UPF), which is in competition with
Cadence’s Common Power Format (CPF).
High Level Design/ESL/C-Based Design
Matlab and Simulink by MathWorks remain the dominant tools for high level algorithm design. They allow
automatic generation of C, VHDL or Verilog from their models, and output scripts for Synopsys or Synplicity.
They also have automatic fixed point conversion for their floating point models.
Synplicity sells a tool called Synplify DSP that accepts a Simulink specification and created synthesizable
RTL for FPGAs or ASICs. It can add pipeline stages, do folding and add channels.
Carbon Design sells C language tools (the symbol for carbon is “C”). They translate Verilog to C for faster
simulation, and feel they compete against emulators and prototype boards. They claim that in one case their
C code was 5X faster than an emulator, plus once you have the C code you can run any number of copies,
unlike expensive emulators. They also have a tool to capture stimulus around the model and replay to a
checkpoint if needed. They have partnered with ARM for a while and now integrate with MIPS as well.
CoWare sells a suite of System C tools that support simulation of System C, VHDL and Verilog and models of
common processors like ARM and MIPS. They say they do “binary to binary” translation for processor
models so they simulate at about 1/10 of real time. They also have the LISA language for describing
processors and also bought the Signal Processing Workshop tools from Cadence, so they have a variety of
tools to support design of an SOC at a transaction level.
VaST Systems sells models for common processors like ARM and MIPS, allowing the user to do virtual
prototyping for software development. These models are cycle accurate at an architectural level and help
with bus structure, cache sizes, etc. Extra logic can be modeled in System C. It can co-simulate with RTL but
only using Mentor and VHDL. Verilog support and support for Synopsys and Cadence simulators are coming
(which is what they said at DAC 2006). In addition to the simulation results, they provide some sort of power
estimate, but there are no ties to any technology so this is based only on the number of events on the high
level signals.
Imperas sells tools for designing heterogeneous multiprocessor systems (a very tough problem). Apparently
they have a high speed simulation environment, some automated way of mapping software onto your various
cores, and debug capability. This is the second DAC where they were in stealth mode and you needed an
NDA to get details (I didn’t sign one). They were in beta last DAC – not clear when they will have a real
product.
Synfora sells a tool called PICO Express (PICO is Program In, Chip Out). The input to the tool is ANSI C with
a few extensions. The tool looks at various hardware ways to implement the algorithm and provides speed
and area information on the various alternatives. The user picks an alternative, and the tool produces RTL,
synthesis scripts and testbenches for the custom hardware.
Critical Blue sells a tool that analyzes your software and creates a custom coprocessor to accelerate the
most common and slowest functions. They emphasize ease of programming a coprocessor (basically there is
no programming) and reuse of existing code as-is.
Forte Design Systems sells a tool that synthesizes RTL (System Verilog) from System C. Registers are
inserted based on latency and throughput requirements in a separate constraint file. In order to know how
much logic it can do in a clock cycle, it characterizes the library for common building blocks. They also have
a tool to synthesize transaction level models, which ties together these three levels of abstraction
(behavioral, TLM and RTL). They also say their tool helps with architectural and hardware/software tradeoffs
for low power. New for this year, it integrates with Magma Blast Create.
NEC sells a tool for behavioral synthesis. As with similar tools, the user creates a library of common building
blocks which the tool uses for initial size and speed estimates. Their tool can synthesize from their extended
version of C to VHDL or Verilog RTL.
Bluespec had a booth but I missed it. They sell two tools for ESL which go from either System Verilog or
System C to RTL, but they emphasize they are not doing traditional behavioral synthesis. They emphasize
that their extensions to the language allow close ties between the coding and the actual implementation.
I missed Mirabilis Design, which sells a tool for high level design that mixes parameterized IP blocks with
System C, Matlab, Excel, Verilog, and C/C++/Java. Their parameterized library contains traffic generators,
statistics viewers, and other components aimed at quick “what if” studies.
Sequence Design says they have teamed with Mentor Catapult to allow power simulation at a System C level.
They say most ESL folks use Power Theater in their flow.
Jeda Technologies sells system C and C++ verification tools. They have defined “Native System C
Assertions” that are similar to System Verilog assertions, and they provide a class library. Their environment
also allows for creating constrained random testbenches, and for defining and measuring functional
coverage. I haven’t tried it, but it sounds like they have an equivalent of Vera or Specman but for System C.
Target Compiler Technologies (www.retarget.com) sells tools for developing custom processors. The
processor is described in the nML language. Their Chess tool creates a C compiler for it, and their Checkers
tool is an instruction set simulator. They support parallelism (SIMD, etc.) for better speed than competing
solutions, they allow profiling and the tool can produce an assembler if desired. They can also produce
VHDL or Verilog form the nML. Now for this year is the ability to insert clock gating.
Synopsys sells a tool called Innovator, which is an integrated design environment for virtual platforms that
allow software engineers to test out code before the hardware models are firm. The user can use either
DesignWare IP or a combination of System C and graphical constructs. The tool creates optimized C++ and
has a hardware debugger, as well as the ability to define a custom user interface. They also sell a tool called
Saber, which simulates physical effects (hydraulic, mechanical, etc.) as well as signal flow algorithms and
software control. It is most commonly used for automotive and aerospace applications.
KETI (Korean Electronics Technology Institute) had a booth that displayed a tool for hardware/software co-
design.
ACE (Associated Compiler Experts – www.ace.nl) sells a tool for generating compilers. You can buy and use
the tool or pay them to create a compiler for you. They also have a set of C code tests that they claim is the
largest test suite in the world – over 1 million independent tests.
Denali Software sells a tool for register management. The input is either IP-XACT (standard from SPIRIT) or
their own format to describe the register map, and the output is RTL for synthesis, C firmware, and code for
verification.
Semifore Inc. sells software for address maps. They have their own language and GUI for entering the
information. Their tool will create RTL, documentation in Word or Frame, and header files, and provides a
single source for all documents (may be similar to Matai Tech but with no IP-XACT output).
Matai Tech sells a tool that reads RTL and lets you input information like register maps, etc. This single
database is then used to create various models (including System C) and documentation, including the IP-
XACT format from the SPIRIT consortium. They may be similar to Semifore (not sure) but Semifore won’t do
IP_XACT.
Beach Solutions sells tools for register management. The inputs are a GUI, and IP-XACT description or
legacy IP (spreadsheets, xml, etc.). It stores all information in an internal xml database and runs about 300
rules on it. The output is driver API, ICE/debug configuration, RTL bus interfaces, RTL system interconnect,
and various documents.
Agilent sells their Ptolemy simulator and last year purchased Eagleware, which allows for easy “what-if”
analysis in the RF design space.
AutoESL Design Technologies had a booth in a hidden spot and I missed them. Based on their web site,
they sell a System C behavioral synthesis tool. It accepts C, C++ and System C and user constraints and
produces RTL and timing/power/layout constraints.
CoFluent Design had a booth that I missed. They sell tools that attempt to create an executable spec. A
functional architecture (before hardware vs. software definition) is defined graphically and with C code, and
simulated in System C.
The Center for Embedded Computer Systems, a research group at UC Irvine, had a booth which displayed
several advanced concepts. One was a NISC (No Instruction Set Computer – beyond a Reduced Instruction
Set Computer). I’m not sure I got this, but it sounded like a super VLIW – the compiler had fine-grain control
of the datapath. A second is the Embedded System Environment. Users write System C programs by
dragging and dropping icons from a library and hence don’t really need to learn System C. They are doing a
third project with the Japanese Aerospace Agency where the user describes a system using Spec C and
component libraries, and the tool creates VHDL or Verilog RTL and software for the system.
Mentor sells a System C debug toolset called Vista that they claim is the most advanced in the industry. They
also sell a tool called Visual Elite that allows users to define a system with System C and RTL, and one called
System Architect that can automatically create TLM models from RTL and lets the user analyze performance
and power. Mentor’s Catapult goes from un-timed C++ to RTL. They emphasize they can take standard ANSI
C but can take System C as well. The user provides timing constraints, and the tool creates VHDL or Verilog
RTL and memories. Unlike the tool from Celoxica (which did not have a booth), Mentor’s inserts registers
automatically so it is probably not as good at what-if analysis or HW/SW tradeoffs. They say it’s best for
dataflow type applications. They also sell a tool for creating libraries for Catapult. Their Platform Express tool
is designed to allow users to design an entire SOC in minutes by dragging and dropping pieces of IP (guess I’
m out of a job). They also sell a suite of tools called EDGE for embedded software and an operating system
called Nucleus. Mentor’s Seamless tool allows hardware/software co-design and supports over 100
embedded controllers and DSP cores.
I missed the Space Codesign booth. According to their web site, they sell a graphical tool that allows
transaction level modeling of your system in System C. They say it facilitates architectural and
hardware/software tradeoffs.
Intellectual Property (IP)
The French firm Design and Reuse (D&R) is by far the largest storefront for IP. They have decided to follow
Google’s lead and give top billing to “partners” when someone searches for IP.
Arm was touting their new ARM11 processor. A multiprocessor version of it can deliver up to 2600 Dhrystone
MIPS aggregate (yes, I know, how do you program it to actually get that). They still sell a wide variety of
ARM7, ARM9 and ARM10 cores and some special cores aimed at secure applications.
Cast (www.cast-inc.com) sells a variety of digital IP, including 32 bit processors that they claim are small and
low power, interfaces like Ethernet and PCI, functions like JPEG and H.264, and encryption cores. They also
sell SOC platform skeletons with timers, memory controller, etc. and software like drivers, boot code, etc. that
the user can customize for their application.
Silicon Hive, a Dutch spin-off from Philips, sells processor IP. They sell an image processor for cameras, a
video processor and a communications processor. All use VLIW architecture, are extensible, and will
generate a C compiler for your customized processor design.
Gaisler Research sells the Leon 3, a 32 bit Sparc V8 architecture processor similar to an Arm-9 that was
developed for the European Space Agency. It has fault tolerant extensions and they say it is a fraction of the
cost of an ARM. New for this year is support for USB and Ethernet.
Plurality (I missed their booth) sells a multiprocessor core and claim they have worked out the
synchronization, scheduling and load balancing such that one can put hundreds of cores on a single chip
with very high efficiency.
Mimosys sells a tool to automatically create extensions for processors or FPGA designs. Note that they do
not create whole coprocessors like Critical Blue, but rather extensions to a processor. The input is C source
code, and the output is Lisa, CoWare or EIA and modified C code. They support a broad range of
processors including ARM, MIPS, Tensilica and various FPGA processors.
Algotronix is a Scottish company that sells AES encryption cores. There are VHDL soft cores that they claim
run up to 10 GHz (obviously that depends on the process you target them to). They also sell tagging
technology for IP. This came from research into side channel attacks (monitoring noise to try to guess a
key). They realized you could also use this on purpose to tag things. They can tag individual pieces of IP on
an ASIC or FPGA, and use a sensor outside the chip to tell what IP is present on the device.
Denali Software sells interfaces for PCI, DDR-SDRAM and Flash. They also sell a NAND Flash management
software suite.
Arasan sells interface IP, including MIPI, Secure Digital, MMC, CE ATA, USB 1.1 and 2.0, Ethernet, PCI, and
AHB. They sell soft IP and were claiming it was “low power”; I’m not sure what that means. They also sell
services (as do many IP companies and vice versa), as well as a few products based on their IP, such as an
SDIO card controller.
Silicon Image sells ATA, SATA and HDMI IP. The digital part is a soft core and the analog is hard IP for
TMSC, UMC and a few other foundries. They bought SiWorks so they now have video codec IP and JPEG
camera IP.
Synopsys provides a ton of IP in their DesignWare but also sells pieces individually. They provide PCI, USB,
UART, and IIC interfaces, as well as AMBA related components.
Mentor sells various interface IP including USB, Ethernet, and various flavors of ATA.
Aldec sells digital IP, including processors, blocks for FTS, cosine, and AES codec, and interfaces like USB
and PCI.
PLDA sells mostly PCI-related IP, including PCI and PCI Express cores, and AHB-PCI bridge cores.
True Circuits, Inc. sells IP, including DLLs, PLLs and SERDES I/O. They now support IBM’s 65 nm process.
Analog Bits, Inc. sells IP. They are best known for PLLs, DLLs and SERDES PHY IP, but they also provide
SRAM and CAM blocks. They are targeted at TSMC, UMC, Fujitsu and IBM/Chartered/Samsung.
MOSAID Technologies sells DDR IP as well as PLLs. New for this year are a DDR3 memory controller, and a
fractional PLL, which has been proven in silicon on the TSMC 65 nm line.
Mixel sells mixed signal IP, including PLLs, DLLs, SERDES, ADC and DAC, and power-on resets. Foundries
supported include TSMC and Chartered.
Dolphin Integration sells digital and mixed signal IP like CODECS, ADCs, DACs, and DC-DC converters.
Lightspeed Logic sells mask configurable logic IP using from 2 to 6 masks. They say that for higher mask
counts they are within 10-20% of the density of standard cells. The IP is targeted primarily at TSMC. They
also sell some reconfigurable IO.
I missed the booth for ViASIC, which sells a gate array type fabric that can be configured in 1 or 2 masks.
They say this allows easy fixes to SOCs with minimum mask costs and also easy creation of derivative
designs.
Sarnoff Labs sells ESD protection IP, targeting the fables market. They use shuttle runs with UMC, Tower,
Fujitsu and Epson (among others) to prove their technology.
Interra systems sells software for digital media, such as MPEG.
Magillem Design Services sells a database management system that they customize for your design flow so
that you can create the standard IP-XACT description of your IP (soon to be IEEE P1685) that was created
by the SPIRIT consortium. They also provide services to create IP-XACT descriptions.
Matai Tech sells a tool that reads RTL and lets you input information like register maps, etc. This single
database is then used to create various models (including System C) and documentation, including the IP-
XACT format from the SPIRIT consortium. They may be similar to Semifore (not sure) but Semifore won’t do
IP_XACT.
OCP (the Open Core Protocol International Partnership) had a booth again this year. They define standards
so that IP can plug into a standard socket and work as-is (good luck with that). They now have about 200
members. On the horizon are standards on FPGAs, Network-On-Chip (NOC) and debug.
Libraries
ARM sells a wide variety of standard cells, IO and memory compilers for various foundries. They have
recently added support for SOI. They are getting ready to release a 10 Gig PHY for TSMC 65 nm process,
with BIST (using external or internal loopback).
Virage sells complete standard cell and memory libraries at 130 and 90 nm and are expanding their offerings
at 80, 65, 55 and now 45 nm. They say they are not pushing base IO below 90 nm; customers should use IO
from the foundry.
Dolphin Integration sells libraries, I think predominantly for TSMC. They say their libraries have an unusually
small number of cell functions (unusual selling point - ?!?) which makes it easier to swap cells of different
types (different VT, etc.).
Library Generation and Characterization
Prolific (www.prolificinc.com) sells a tool that generates libraries. It accepts a SPICE netlist and produces a
layout using both generators and synthesis (most competitors use one or the other).
Nangate sells tools for library generation and characterization. One tool generates libraries using synthesis
and compaction. A second characterizes libraries and produces models in a variety of formats like Liberty,
Verilog, LEF, GDSII, etc. A third tool analyzes and compares Synopsys Liberty (.lib) files.
Synopsys now owns Cadabra, a tool for creation of library cells from a SPICE netlist. They also emphasize
the ability to migrate cell layouts to new rules, and claim this is the leading tool in the field.
Library Technologies sells a tool for characterizing standard cells, memories and full custom blocks.
Altos Design Automation sells a tool for library characterization. They claim it is extremely fast
(characterization involves an enormous number of SPICE runs) and supports a wide variety of formats,
including Liberty SI, ECSM and CCM.
Z Circuit Automation (www.z-circuit.com) sells a tool for library characterization, including differential inputs
and dynamic logic. New for this year is support for statistical timing (CCS and ECSM). They are an In Sync
partner with Synopsys. They also sell a tool to check libraries. The input is a SPICE model, constraints, a .lib
file and Verilog models. It checks for consistency between the models and also does basic sanity checks.
Magma sells a library characterization tool that uses their new FineSim simulator. They say it is able to
handle inter and intra cell variation to accurately model On Chip Variation.
Simucad (Silvaco) sells a tool for library characterization. Although they interface to HSPICE and ELDO, they
say that they have a speed advantage when using their own SmartSpice simulator because they are so
tightly coupled.
Fenix Design Automation sells a tool for checking libraries. The input is various representations of the library
(dfII, Open Access, Milkyway, Verilog, Liberty, LEF, GDSII, SPICE, etc.). It checks for things like consistent
pin names, abstract consistent with layout, consistent timing, etc. They are working on reading a Magma
database. They also have a tool to compare the timing in Primetime to that in Cadence Encounter and PKS.
OEA sells a tool for cell level parasitic extraction. It generates an accurate cell level SPICE netlist from a
layout.
Memories
Virage sells a variety of memories and memory compilers. They say they can produce different varieties
aimed at high speed, high density or low power, but customers typically want the right combination of the
three. The absolute lowest power memories will be larger and people often aren’t interested in that. They
emphasize that they don’t release information about how the logical addresses for their memories correlate
to the physical location, so other vendors can’t test them as well. For example, they claim that a
checkerboard pattern from LogicVision may not be a true checkerboard on the physical memory. Virage also
sells a non-volatile memory at 0.18, 0.15 and 0.13 micron feature sizes for chip ID type applications.
eMemory (www.ememory.com.tw because Denali owns www.ememory.com) sells nonvolatile memory IP, both
One Time Programmable and Flash. They sell instances, not compilers. They have a catalogue of existing
instances and if you want something else it will cost you some NRE. They say their memories work with most
foundries, including Chartered, TSMC and UMC.
Kilopass sells non-volatile memory instances. Theirs are only One Time Programmable (no flash) and use 90
nm and 65 nm CMOAS technology. They are obviously aimed at secure applications like smart cards; they
emphasize that the memories can’t be read by voltage contrast SEM and are radiation hard.
Dolphin Integration sells low power RAM instances that they say are also very dense.
Novelics sells memory IP. They sell SRAM, register file, ROM and CAM, all standard CMOS, for TSMC, UMS,
SMIC and Silterra. The sell either instances or compilers. They emphasize low power and high speed.
Silicon Design Solutions sells embedded memories, both instances and generators. They provide SRAMs,
ROMs, register files and CAMS. They say they have working silicon at 45 nm. They support TSMC,
IBM/Chartered/Samsung and Siltera. Their engineering is done in Vietnam (look out India).
Micro Magic sells an intelligent tiling tool that can be used to generate SRAMs, DRAMs, CAMs, ROMs,
register files, etc. from pre-existing leaf cells. Note that they do not provide leaf cells; you need to do that.
They said some people use standard cells and are still able to generate memory layouts that are denser and
faster that if the layouts were done with place and route.
Innovative Silicon had a booth touting their Z-RAM technology but it was only available for licensing by
memory vendors; it was not a product. This is a DRAM with no capacitor (it uses the floating body effect of
Silicon-On-Insulator technology). They say it is both faster and denser than normal DRAM technology.
Legend Design sells a tool for memory characterization. It automatically extracts critical paths from RAMS
and then uses their own MSIM SPICE simulator to do Monte Carlo characterization.
Design Entry
National Instruments, which sells hardware and software to turn your PC into a basic tester, also sells design
software. They have a graphical tool for design entry and SPICE simulation called Multisim, which comes with
a library of over 12,000 components. LabVIEW also does digital design. The code is entered graphically; it
creates VHDL internally and uses Xilinx tools to design hardware to implement that function. Another tool
turns graphical input into C code for common processors. They were proud that their software is used in
Lego MINDSTORM.
Aldec sells a design entry tool that includes graphical editors, wizards and a language sensitive editor for
VHDL, Verilog, and C/C++./Handel-C/System C.
Mentor sells a tool called HDL Author that allowed graphical, tabular or textual entry of RTL.
Functional Verification
I attended the Cadence top down verification demo, which was nearly empty. Synopsys is pushing their VMM
methodology for System Verilog, and Mentor is pushing their AVM. Cadence bought Verisity, whose
Specman competes with System Verilog, so they are a “me too” in System Verilog. They emphasized breadth
and talked about mixing System Verilog, System C, and emulators. At another Cadence talk, ST talked about
actually doing simulation like that. They said parts of System Verilog are hard, particularly the object oriented
parts. They thought that the most easily accessible parts are randomization and constraints, interfaces and
maybe assertions. Some Cadence-speak terms: SVM – system verification methodology (based on the
Verisity methodology), URM – universal reuse methodology (based on Verisity’s ERM), UVC – universal
verification component (based on Verisity’s UVC). Their URM is their competitor to VMM and AVM, and they
provide free source code and free licenses for it. They claim anyone can simulate it, unlike VMM, which has
hidden source, and AVM, which uses constructs that are legal but not all simulators can compile. They said
they still plan to support Specman because it has a many users, and are looking at mixing Specman’s e
language and System Verilog.
Formal Tools
Mentor’s 0-In division has an interesting tool that checks for assertion density. Ideally, designers add
assertions as they write the code, which act as a sort of executable specification describing their intent when
writing the RTL. In the real world, that doesn’t always happen. Some tools also add obvious assertions to the
code. This tool checks whether it thinks there are enough assertions in a piece of code. Obviously you would
expect more assertions for control logic than for simple data paths. I do not know what smarts the tool has in
deciding how many assertions to expect.
Calypto sells the first sequential equivalence checker. Their tool can compare designs with different pipeline
lengths, different state machine implementations, etc. New for this year is power optimization using
sequential understanding of the circuit. They claim the clock gating is done at RTL level and is
complementary to the clock gating inserted by combinational tools.
One of the dirty little secrets in full formal tools is that they won’t always work and you can’t always predict
when they won’t. They try to go through all possible combinations, and in some situations there are simply
too many of them (state space explosion). For reasonably large circuits, tools are limited to exploring a few
tens to a few hundreds of clock cycles from the starting point. A key question then becomes how to find a
good starting point, but this has not been addressed well.
Two years ago Jasper Design Automation originally sold a product for serious verification engineers that
they claimed was guaranteed to get a solution. The designer himself snips away states he doesn’t care
about, based on information the tool gives him about counters, FIFOs, etc. and that allows the tool to
examine more useful states that took more clock cycles to get to. Last year they decided this was too hard
for non-power users so they renamed their original product “Deep Formal” and introduced “Formal Light”,
where the user just picks the number of clock cycles or amount of CPU time he is willing to wait for an
answer, and the tool either comes up with an answer or hits that limit. New this year is “In Formal”, which
sounds one step farther removed from the power user. The user specifies a trace he would like to see, like “I’
d like to see an address collision”, and the tool creates inputs to generate that trace. Harry Foster is no
longer with the company and he originally envisioned the tool as a way for an engineer to understand a new
design by viewing traces rather than staring at code; he was surprised at the way it was being sold. Their
tools can accept VCD to get the design to an interesting state for the formal engine to go exploring, but they
say users almost never use this feature and instead start from reset, which of course severely limits what
states it can explore before running out of gas. They also have a tool to create a test plan.
Real Intent has a tool for early automated checking of RTL, even before it is complete or has any
testbenches. It generates assertions (no user assertions) and checks for things like dead code. They have a
second formal tool that checks for user assertions, which they assume will come later in the design flow.
They have a third tool that checks clock domain crossings.
Averant sells a property verifier that accepts System Verilog, OVL or PSL assertions. Formerly they were
selling their own language as well which they said many customers preferred, but they were talking only
about standard languages at this DAC. Their tool can perform automated checks (deadlock, clock domain
crossing issues, etc.) and can check for user-supplied properties. They also have libraries of assertions for
standard bus protocols (ARM protocols in particular) so they can check that your bus interface is correct
without needing any simulation. They say they are the only tool set approved by ARM for this purpose.
OneSpin Solutions sells two formal tools. The first is a property checker, which is unique because they claim
it checks whether the property specifications completely describe the function of the block. If the
specifications are not complete the user can add more properties as directed by the tool. The second tool is
an equivalence checker that they say is better than some competing tools because it is not tied to tools used
to create the design. New for this year is an FPGA equivalence checker.
Axiom (formerly @HDL, hence www.athdl.com) sells their original formal tool, which checks for things like
FSM deadlock and code reachability. They also have a clock synchronization checking tool. Neither seemed
to be the focus of their DAC booth; they were selling their simulator much more heavily.
Cadence sells the old Verplex tools as Conformal. Their equivalence checker has a reputation for being
easy to use. Their Incisive Formal Verifier does automatic extraction of common assertions (like dead code,
FSM deadlock, etc.) or takes user assertions in PSL, SVA or OVL.
Synopsys sells Formality, their equivalence checker. They emphasize that it interacts with their synthesis
tools so it can understand things like inserting or moving pipeline registers.
Mentor sells an equivalence checker called FormalPro.
Magma sells an equivalence checker based on IBM’s internally developed tool. It does not seem to be
heavily advertised.
Semi-Formal Tools
Mentor’s 0-in division sells a semi-formal tool. It takes a simulation and uses formal techniques to search for
problems in states that are close to states reached during the simulation. That reduces the problem of state
space explosion and is different from Synopsys Magellan, which creates its own simulation vectors. They say
their full formal tools sell better than the semi-formal one.
Synopsys sells a tool called Magellan that combines simulation and full formal techniques to search for
problems many thousands of clocks from the starting state. It uses simulation (using stimulus it generates
itself) to get to an interesting neighborhood and then explores that neighborhood exhaustively using a formal
engine. Star Trek fans might think of using warp drive to go from star system to star system and then
exploring each star system with impulse power.
Synopsys sells a tool called ESP for equivalence checking on memories. They sell it as being complementary
to Formality, which can check logic. I believe it is based on the symbolic simulator technology they got from
Innologic. Innologic also had some very interesting and powerful general purpose technology, but it was
nearly impossible to explain to anyone because it was so foreign and I doubt it will ever find a wide audience.
It’s probably one of those tools salesmen avoid selling because it will take too much support.
Clock Domain Crossing (CDC) Tools
This was one of the areas that John Cooley thought was finally reaching maturity.
Mentor’s 0-In division sells a clock domain crossing tool. They say it does 1. static CDC analysis 2. Protocol
verification (it can add assertions automatically if desired) and 3. Reconvergence verification.
Many other vendors have tools for checking clock domain crossing and are listed above.
Simulation-based Verification
Synopsys continues to sell Vera as well as pushing System Verilog. It seems hard to believe they would sell
competing tools and methodologies indefinitely but currently that is their claim. Their Verification
Methodology Manual (VMM) for System Verilog provides a great infrastructure for creating a verification
environment, but is not useable with any other simulator.
Last year Cadence said that Specman (acquired when they bought Verisity) will be around for years
because of the large user base, but they saw it eventually being replaced by System Verilog. They are
behind Synopsys and Mentor on the System Verilog bandwagon, and this year they seem to be emphasizing
that they have every flavor of simulation-based verification. They have Specman, System Verilog, System C,
and big honkin emulators. It sounds like they’re hedging their bets.
Breker Verification Systems provides a way to do testbenches graphically (or textually in C/C++, or both).
The methodology was originally developed at AMD. The tests are done mostly using BNF, which is commonly
used to define the grammar of a language. They say their tests are directed but you can randomize the
graphs; not sure what that means. In one customer testcase, they say they took a 15M gate design that had
already been verified, using 190K lines of code for a layered testbench and 165K lines of directed tests.
They claim that in a few weeks their lone AE was able to create a graph with 1700 nodes that got equivalent
coverage. They also do coverage graphically, which they say is easier to understand. They see themselves
as a step above System Verilog.
Certess sells a tool that attempts to answer the fundamental question in verification – how do you know when
you’re done? They use a process they call “mutation analysis” where they insert faults in the RTL and
measure coverage of those.
I missed the Nusym booth but checked the web site. They sell a tool that will automatically generate vectors
that attempt to achieve 100% code coverage. It also does analysis of your design to show why some parts
can’t be covered.
Mentor sells 0-In CheckerWare, a large set of parameterized assertions. You could write these yourself but it
might take weeks to create some of them.
Obsidian Software, Inc. sells a tool called Raven for processor verification. The user defines various
templates for expected behavior of the processor, and the tool then randomizes various registers, processor
states, etc. to help verify that behavior. They say a few hundred templates can be used to generate millions
of tests.
Avery Design Systems sells verification environments for the bazillion variations of PCI and ATA. They also
sell a tool called TestWizard that sounds like Specman or Vera (directed random tests, PSL assertions,
functional coverage) but does not require any new language. Tests can be written in Verilog, VHDL or
C/C++. Their tool bolts onto your simulator.
Axiom (formerly @HDL, hence www.athdl.com) recently bought an Indian services and tools company and
acquired Protometer, a tool for monitoring standard bus interfaces. The tool watches the interfaces and
measures functional coverage and helps with transaction level debug. The have monitors or some standard
buses and are creating a larger library. The user can also write an xml-like file (CDF format) to describe a
new interface, and the tool can measure functional coverage and can create random sequences to achieve
coverage goals.
Denali Software sells verification IP to verify compliance with a number of standard bus protocols, including
ASI, AMBA, ATA, Ethernet, PCI Express and USB. They also sell verification IP for various types of memories.
Linters
A lot of simulators now come with free linters so the standalone products are usually more than just a linter.
They usually have some formal verification smarts to them and are often sold by a different name like
“predictive analyzer” or “RTL analyzer”, to distinguish them from the free tools.
Atrenta sells Spyglass, which has some fancy algorithms under the hood (synthesis and formal checking
included) so they don’t like the term “linter”. They claim they beat 0-In with their clock domain crossing
checks. They also sell a tool called 1 Team System for analysis of System C code, and claim they do much
more than simple lint checks.
Synopsys sells a linter called Leda, which does the usual checks on coding styles, DFT rules and reuse
rules. It now has low power checks.
Blue Pearl Software sells a tool called Indigo that does normal linting checks like those for DFT and reuse,
and also checks for clock domain crossing errors. They say they are now working with Magma. Last year
they told me it does not do synthesis like Spyglass so it runs faster.
VeriEZ Solutions, Inc. sells a tool that does linting of System Verilog or Open Vera, including assertions and
testbenches, including checking for VMM compliance. They also sell a translator from Open Vera to System
Verilog.
Veritools sells a linter for Verilog, VHDL and System Verilog. They say it uses a combination of formal and
structural analysis, which sounds like Spyglass. It checks for reusability and for clock domain crossing
issues, among other things.
Code Coverage
Conspicuous by their absence was TransEDA, which sells a code coverage tool. They went out of business
and then came back but apparently did not feel their limited resources were best spent on a DAC booth.
Many simulators now come with a free code coverage tool, and it’s tough competing against something that’s
free. Of course, most simulators also come with a debug tool but Novas does just fine selling their high
priced debug environment. I’ve compared the TransEDA tool to the code coverage tool that comes free with
Cadence Incisive, and while the Cadence tool is basically usable, the TransEDA tool is clearly superior. I’m
curious why Novas can make it but TransEDA is having problems. It may have to do with the fact that
debugging a simulation is a make-or-break high priority job while code coverage is a check in a box to make
your manager happy.
Simulators
Mentor says Questa (formerly Modelsim) is now responsible for 30% of their verification revenues, and there
have been more than 4000 downloads of their free “Advanced Verification Manual”. They say Questa is
native compiled, uses a single event timing wheel for all languages, has a single kernel, and enough
capacity for NVIDIA to simulate a chip with 681 million transistors. New for this year is Verilog encryption. Also
new is power-aware simulation. It can now simulate a chip powering down a block and bringing it back up,
and understands things like retention flops and isolation cells. The power intent is done as a UPF (Universal
Power Format) file which is read into Questa and translated into their own format. They say it will be used
natively by the end of the year. Mentor also sells a tool called ADVance MS for mixed signal simulation.
Cadence renamed NC-Sim to Incisive and they now have three flavors of it. The basic flavor will do Verilog,
VHDL, System Verilog design constructs, has their GUI and code coverage tool. The Incisive Design Team
Simulator adds functional coverage, transactions, assertions, System Verilog testbench constructs, System
C, and what sounds like a linter (hard to tell from the glossies). The Incisive Enterprise Simulator adds e and
a “Scenario Builder” and “Verification Manager”. It sounds like if they get rid of Specman they can no longer
sell the highest priced option.
Synopsys VCS has historically been a strong competitor in Verilog but their VCS-MX product has historically
been weak in VHDL; I’m not sure if that is still true. They now provide verification IP just like they provide
design IP with their synthesis tool. This sounds very smart; it makes legacy verification environments hard to
port to another simulator.
Liga Systems sells an accelerator for RTL (their specialty) or gate level simulation. It is a VLIW processor
aimed at RTL simulation. It happens to be implemented on an FPGA but this is not an emulator. They can
compile the RTL equivalent to about 10M gates in an hour, and the board holds the equivalent of up to
300M gates. They co-simulate with Mentor or Cadence and they claim 10X to 100X speedup because they
accelerate the whole language (even the testbench), not just the synthesizable portion. Gate level simulation
is without timing.
Dolphin Integration sells SMASH, which allows a mixture of System-C, VHDL, Verilog and SPICE. It does
power simulation, transient noise (and jitter) and they say it can help with yield enhancement analysis (it
uses Monte Carlo simulations to identify transistors with problems). It also supports power and leakage
simulation but currently just for digital circuits.
Axiom (formerly @HDL, hence www.athdl.com) sells a simulator that can mix System C, System Verilog and
Verilog. They say it was architected from the ground up to use multiprocessor systems for maximum
simulation speed. It also supports PSL and OpenVera, and comes with a programmable linter and a debug
environment.
FTL (faster than light) Systems sells a simulator that they say can co-simulate C, C++, System Verilog,
Verilog AMS, VHDL, VHDL-AMS, and SPICE.
Aldec sells an inexpensive single-kernel simulator that they say accepts C/C++, system C, System Verilog,
VHDL, Verilog, EDIF netlists, and assertions in various formats. They can co-simulate with Matlab and
Simulink. Their simulator includes a linter. They can also prototype designs in an Actel FPGA. They can
capture waveforms and generate a testbench from them.
Avery Design Systems sells software to partition a simulation onto multiple CPUs, but uses standard
simulators like VCS, Incisive/NC-Sim, and Questa/Modelsim. Last year they said that NVIDIA did one
simulation where the time dropped from 20 hours to 3 hours. They said customers typically used 5 to 8
processors for RTL and 10 to 15 for gate level simulation. Given that all the major simulators are being re-
written to be multi-threaded, I would be curious if they can somehow provide an advantage over what is built-
in.
Debug Environments
Novas sells the Debussy and Verdi tools for debug. Debussy is for gate level, Verdi allows RTL debug as
well. New for this year are support for System Verilog assertions and a new temporal viewer. Their have a
tool called Siloti which compresses waveform databases by saving only “essential signals” (maybe 20% of
them) and calculating the other signals on the fly.
Veritools sells a debug environment for VHDL, Verilog, System Verilog and (new this year) System Verilog
assertions. They say it is faster than Debussy/Verdi and only 20% of the cost. The new assertion debugger
displays assertions in the waveform window and allows “what if” analysis to determine the cause of the
failure. It accepts analog input as well and they say it will tie directly to HSPICE within a month after DAC
(sounds like someone missed a deadline).
Emulators, Hardware Accelerators, Prototyping Boards, etc.
Cadence continues to sell their two formerly competing lines of emulators, Palladium (acquired from
Quickturn) and Xtreme (acquired when they bought Verisity). The smaller Xtreme boxes are rack mountable
while the giant Palladiums are standalone. The Xtreme boxes can model tens of millions of gates while the
Palladiums can do hundreds of millions. Both are also compatible with System C, C++, e, and assertions in a
variety of formats.
Mentor sells their Veloce and VStation Pro lines of big box emulators. They say they can emulate up to 128M
ASIC gates, compile about 15M gates/hour, support SVA, PSL, OVL and 0-In CheckerWare assertions, and
claim 10% visibility without recompiling. They also sell a tool called Testbench Xpress that you to use a
transaction level testbench to communicate with the emulator. Less communication means faster emulation.
They also allow you to add various processors (such as ARM7, ARM9 and ARM11) to the accelerator using
“iSolve”.
The Dini Group emulator boards are now based on Vertex 5 FPGAs. They can fit up to 12M ASIC gates per
board and have DIM sockets for memories. They say the interconnect will run up to 450 MHZ but the speed
of your emulation depends on your circuit.
Hardi Electronics (purchased by Synplicity) sells stackable prototyping boards with up to 4 Virtex-5 parts (8M
ASIC gates) per board. I/O runs up to 200 MHz and internal signals up to 400 MHz. They were very proud
that all signals on a single connecter were routed to within 50 ps of each other.
Gidel sells prototyping boards with up to 6 M ASIC gates per board, up to 100 M gates per system. The
boards operate up to 200 MHz.
Eve (www.eve-team.com) sells an emulator on a PCI card that plugs into a PC and can emulate up to about
6M ASIC gates, and big boxes that can emulate up to 100M gates. They also bought Tharas, which is (I
believe) the only real hardware accelerator company left. The AE at their booth thought the Tharas boxes
were aimed at really large designs.
A German company called ProDesign (www.prodesign-usa.com) sells emulator/prototyping boards called
CHIPit. They can emulate up to 21 M gates at up to 200 MHz. I believe they sell less expensive boards with
no debug capability, for use by software developers after the hardware folks have a working netlist.
GateRocket sells an FPGA board that plugs into a PC and integrates into simulators from Mentor, Cadence
or Synopsys. Board options include one with a Virtex-4 LX-200 or a Stratix II 180. They say the Altera board
costs about $25K and the Xilinx one about $30K. Place and route is done with vendor tools. They support
Verilog or VHDL or mixed language at the lowest level.
Dynalith had a booth but I missed them. They sell an FPGA prototyping system on a PCI card that co-
simulates with Questa/Modelsim, Incisive/NC-Sim, and VCS.
ForteLink sells a small FPGA box for emulation or in-circuit simulation. They have their own tool, optimized
for their box, for partitioning the design.
KETI (Korean Electronics Technology Institute) had a booth that displayed an FPGA based emulator board.
Synplicity sells a tool that aids in partitioning a design into multiple FPGAs. This is often a problem when
trying to prototype an ASIC on FPGAs. Sometimes the ASIC design is inferior because of the constraints
needed to partition it onto multiple FPGAs.
Low Power
I attended the Synopsys Low Power lunch on Monday. TSMC is now using adaptive voltage scaling (AVS) on
a 45 nm test chip, as well as using lower VDD for memory bit cells versus memory periphery. Their reference
flow now uses the $power and $isolate tasks that Synopsys donated to the world. Adaptive Voltage Scaling is
where you have a speed measurement circuit on your chip and you are constantly playing with the voltage
so that you are only giving it enough juice to just barely work at your current clock frequency (which may be
variable). I’ve never done a design with AVS but I have several concerns, including how well standard cells,
memories and level shifters track each other speed-wise as the supply voltage changes, and how you would
simulate and (perhaps worse) test the feedback system between the speed measurement system and the
voltage regulator. ST uses pulsed latches and dynamic voltage and frequency scaling (DFVS) and power-
width modulation (PWM). For “pulsed latches”, you use one edge of the clock to generate a narrow pulse,
which then goes to the enable of a latch. If the pulse is narrow enough, it is almost like having an edge
triggered device. Because a single latch has less loading on the enable line than a master-slave flip flop
(which is actually two latches) has on the clock line, you can save power this way, although it complicates
timing analysis a bit and can’t be done on every flop. DFVS means that you have sets of clock frequencies
and voltages, and works well in cases where you know in advance what your workload will be. If you have a
small queue of things to do, you can drop your voltage and clock frequency to save power. Because DFVS
uses fixed frequencies and voltages, it is easier to verify than AVS. ST said their chips now typically have
about 30 clock trees. They said Design Compiler does about 80% of the clock gating automatically. They do
post placement insertion of HVT (high threshold voltage) cells to minimize leakage, and can have up to 80%
HVT cells and up to 7 different power domains. They do domain description at the RTL level and insert
isolation cells during synthesis. An Analog Design DSP group talked about using VCS in “power aware”
mode. They found errors and had to change the behavioral models for power-up and power-down. The RTL
also had to be changed to spot ‘X’s, which are normally ignored at that level (linters hate when you check for
‘X’).
I also attended the Synopsys/ARM low power lunch on Wednesday (cold lunch, of course). Synopsys is now
pushing a book called the Low Power Methodology Manual. ARM and Synopsys did a low power test chip
called SALT. One issue they discussed is restoring state in a block that has been shut down and powered up
again. They said you need to analyze the power cost of restoring state; you may be saving less power than
you think. One option they discussed was doing a checksum of internal states to see if the save/restore
disturbed the states. One very interesting thing they said was that leakage power savings seemed to be
greatest at about 35 degrees C; at higher temperatures the power switches started leaking. In addition to
power gating, they used non-minimum gate widths, stacked transistors, and back biasing to control static
current. They found that distributed switches worked best with rings around old IP. They said that speed and
power must be optimized concurrently.
I also attended a Cadence low power presentation. They bragged about being in the TSMC reference flow.
Their flow for low power is (1) write CPF (common power format) to describe power intent (2) check the CPF
using their Conformal LP tool (3) plan power simulations (done in Incisive/NC-Sim) which involves defining
coverage metrics for power modes (combinations of blocks that are “on” or “off” or at different voltages) (4)
do RTL simulations (5) synthesis of level shifters, isolation cells, etc., based on CPF, though some people
instantiate these themselves (6) simulate gates, check power, look at coverage (7) check again with
conformal LP. They emphasized that all power information is in the CPF, not the RTL, so you can’t screw up
the power intent when modifying the RTL. The separate file also allows “what if” power analyses without
modifying the RTL. Power estimation is done from TCF or SAIF activity files. They said that for large designs
the problem is gathering the information for the CPF file, not writing it. They also said CPF for gate level has
a lot more information than CPF for RTL. They said CPF for Simulation of in-rush current is done in
VoltageStorm, and they are currently working on simulation of power-up. They are also working on automatic
generation of assertions; currently the user must write their own. Some Cadence acronyms: PSO = power
shutoff, SR = state retention. Note that CPF is an Si2 standard, but there is a competing Accelera standard,
UPF (Universal Power Format). Cadence was definitely feeling the heat from the other vendors (including
Synopsys, Mentor, Magma, ArchPro and Axiom) who were pushing the UPF. They had a number of posters
at and near the convention center that read: “Low Power Leaders Use Cadence Low Power solution (and
they’re using it NOW) – CPF – Open, Inclusive, Real – download@www.si2.com”.
I attended a Synopsys low power presentation. They said one of their customers told them the low power
considerations on one of their designs literally doubled the schedule versus ignoring power. I compared it to
Cadences flow and it has pluses and minuses. One minus is that there is no concept of “coverage” of power
scenarios (combinations of blocks that are on or off or at different voltages). On the plus side, DC now does
a lot of static power checks automatically, and they can optimize delay for all power scenarios
simultaneously. Formality also now understands power issues. They recommend scan compression to
minimize the interfaces between voltage domains.
Synopsys Power Compiler supports automatic clock gating. Techniques for minimizing static power are
handled by other tools.
ArchPro Design Automation sells tools for low power analysis and synthesis. Their MVSIM tool works with
simulators from Mentor, Cadence and Synopsys to verify multi-voltage designs, and can handle arbitrary
hierarchy, including nested islands and domains. Their MVRC tool is an equivalence checker for multi-
voltage designs which can verify the design for all power management states. MVSYN does synthesis of
multi-voltage designs and they claim saves man-months of scripting and hand edits. It also has ECO
capability and supports “what-if” analysis. They talk about much more subtle bugs than their competitors. I
don’t know if competitors are just keeping the examples simple (perhaps) but the impression one gets is that
if one wants to be certain a low power design will work, these are the tools to use.
Sequence Design has several tools for low power design. Their Power Theater tool allows power estimation
at the RTL level. It allows RTL level power optimization, where they say the greatest savings are possible. It
now understands multi-VT design and power gating. Dynamic Frequency/voltage Scaling is coming, but
Adaptive Voltage Scaling is pretty far down the road. Their CoolPower tool allows simultaneous analysis of
supply drops, timing, power, signal integrity and electromigration, and has an option to analyze power gating.
Their CoolPower tool can insert power gating, aids with inserting decoupling capacitors and minimize power
by swapping cells.
ChipVision sells a tool called Orinoco. It is aimed at allowing SOC architects to minimize power in the
datapath architecture. They claim several customers have had power savings of greater than 70% using
their tool.
Forte Design Systems sells a tool for synthesis of RTL from System C. They say it also has some smarts to
help with architectural and hardware/software tradeoffs to minimize power at the RTL level.
KETI (Korean Electronics Technology Institute) had a booth that displayed a tool for system level power
analysis. I didn’t get details.
Atrenta sells a low power version of Spyglass. They say they can estimate static and dynamic power using
either UPF or CPF (they have a translator!) and they do low power checks. They can also automatically fix
some problems, like lack of level shifters or isolation gates.
BullDAST (DAST = Design Automation Services and Tools) is an Italian company that sells tools for low
power design and analysis. One tool they were showing is used for sleep transistor insertion. It automatically
clusters gates, estimates peak currents and sizes sleep transistors accordingly, and creates sleep control
logic. The input includes a placed design and the output includes a modified placement allowing routing of
power to sleep transistors. They also sell an RTL power estimator, a tool for partitioning large memories into
smaller ones to save power, a tool to encode bus transfers to save power, and tools for smart clock gating.
Apache Design sells a version of RedHawk called RedHawk-LP for low power analysis. It can perform static
and dynamic analysis of blocks with clock gating, multiple threshold voltages, multiple supplies, and power
gating.
Cadence sells Conformal Low Power. Unlike their normal version of the Conformal equivalence checker, this
takes only a single design as input and uses formal engines to check it. They check they listed sounded
much more ordinary than the ones listed by ArchPro, although the presenter said it was only a partial list.
Mentor’s low power checking currently checks retention flops. Isolation cells must be placed in wrappers but
will be handled directly later. They say their customers are more concerned about retention flops than
isolation.
Magma uses UPF for low power implementation and also does checking for basic problems. They team with
ArchPro and Axiom for more sophisticated checks. They say their tool will insert clock gating, use high
threshold cells where possible, insert fine grain or course grain power switches and handle the new nets,
insert isolation cells and level shifters, do power-aware clock tree synthesis, automatic power grid synthesis
and automatic insertion of decoupling capacitors.
Envision Technology (www.envision-tech.net – not an easy one to Google) presented a lot of stuff about
power management, voltage islands, static power, etc. but currently has only a single product, which is a
piece of IP for gating clocks. If I understood correctly, it checks the inputs to a block and if they don’t change,
it disables the clock, on a clock-by-clock basis. I’m curious what the timing impact on the design is, since the
input to a block can change just before the active edge of the clock.
Proficient Design sells gate level low power IP and tools to insert it. They have larger low power blocks
(adders, multipliers, wide registers) that they insert after synthesis. They currently support TSMC 130 nm
and 90 nm, 65 nm is coming.
Prolific (www.prolificinc.com) sells a tool that reduces power by swapping in low VT cells. They claim that
even if you have already told other tools to insert low VT cells, theirs will insert even more. It uses Primetime
for timing analysis so there are no arguments about whether it still passes timing.
Incentia sells a logic synthesis and optimization tool that is DFT aware and they claim is better at low power
optimization than standard tools. They claim the low VT cells it inserts can improve power by 10-15%, even if
another tool has already attempted optimization for low power.
I missed the booth for Golden Gate Technology (not to be confused with the Golden Gate simulator that
Agilent bought). They sell a tool for power reduction that uses a number of unique techniques. They take a
working, routed design and reroute it to minimize the capacitance that will be switched. Starting with the most
active nets (including the clock), they route from the top levels down to minimize capacitance. They say that
after this step, net capacitance is lower on many nets so high VT cells can be inserted to reduce leakage
current. They also sell what they say is the first tool for power planning (that’s their claim). It supports multi-
voltage-island design, implements level shifters, calculates IR drop and implements the power grid. They say
it has been used on more than 50 tapeouts.
Static Timing Analysis
One big issue here is the IBM “temperature inversion” issue, which I assume exists for other foundries as
well. As you cool down a transistor, several things happen. First, the molecules stop jumping around so
much, so it’s easier for electrons and holes to move through them (the mobility goes up). Second, the
threshold voltage goes up, which means you need a higher voltage to turn on the transistor. These two
effects theoretically compete, but in the real world the mobility has always been more important, so cold=fast,
hot=slow (at least until now). In order to minimize power, designers now use transistors with very high
threshold voltages, which will have less leakage current when they are off. IBM recently discovered that for
some of these transistors, the effect of temperature on threshold voltage is more important than the effect on
mobility, so for them cold=slow. This means that some of the gates on your chip will be slowest at high
temperature and some at cold temperature. The first problem is that it takes a ton of simulation to
characterize a library for a certain set of conditions, so many libraries have not be characterized at cold
temperature, low voltage, worst case process because historically no one has cared about this combination.
The second problem is that the delay versus temperature may not be linear or even monotonic; maximum
delay may occur at some random temperature between min and max. If you know the delays for your gates
are greatest at either the highest or lowest temperature and they vary linearly, then if you just calculate the
delay for those two cases you are guaranteed to get the worst case delay at one or the other temperature.
BUT if the delays are nonlinear with temperature, then you have no idea what temperature to run to get the
worst case delay on a path. Anyway, I talked to the Synopsys Primetime AE who was at DAC and he said
they can’t deal with temperature inversion and he has no idea when they will be able to. I haven’t found
anyone else who can deal with it, either.
Synopsys Primetime is still the most common signoff timing tool. The new Primetime VX is the process
variation aware version that requires a separate license. There is also a Primetime SI and a new Primetime
PX which are discussed separately. They also have a new tool called NanoTime that sounds like an
improved version of Pathmill. It is a SPICE-like transistor level static timing analyzer that they claim is within
5% of HSPICE and can handle signal integrity effects.
Incentia sells what they claim is the fastest STA tool in the world. It can do multi-corner, multi-mode analysis
and has a special way of handling On-Chip Variation (OCV) where they look at the physical location of gates
to minimize pessimism. They also have a tool that will check constraints, optimize the constraints you write,
and debug your constraints.
Extreme DA sells a variation aware static timing analysis suite called GoldTime. Their tools can create a
statistical library, do a variation aware RC extraction, perform variation-aware static timing analysis (nominal,
statistical or Monte Carlo) and can also interface to major back end tools for optimization. They say their tool
only keeps the data it is currently using in RAM; the rest goes to disk. This makes it faster for large designs
and facilitates multiprocessing. They claim to have done a design with 27 million placeable instances in 1 ½
hours.
Magma sells a statistical timing analysis tool (Quartz SSTA) that they claim accurately models the effect of
timing variation without being overly pessimistic. I’m not sure how closely tied the tool is to the Magma flow
versus being a point tool.
CLK Design Automation had a booth but I missed it. They have tools for static timing analysis and also signal
integrity analysis that they say are faster for two reasons. First, they are multithreaded with very low
overhead for adding additional processors. Second, they say their tools are incremental, so while iterating to
fix bugs, they analyze only the changes to the design.
Fishtail Design Automation sells tools to both check and generate timing exceptions in RTL. The problem
with doing them by hand is that you can miss some and get bogus timing errors, or worse yet cause the tool
to ignore real errors. They also have a product (that I believe is unique) that manages constraints through
the design process. It handles name changes, hierarchy level changes, etc. so that a single set of golden
constraints is used for the whole process. Last year they were far and away the leaders in constraint
generation; I’m not sure if they are still top dog.
Blue Pearl sells a tool called Cobalt that generates timing exceptions from RTL. As with competing tools, their
tool sometimes generates a lot more exceptions than a human would and they say it is hard to guarantee all
tools will recognize and properly use the constraints. They have a tool called Azure which is still in beta (it
was advertised at DAC2006), which checks timing exceptions. They say it uses a completely different
algorithm than cobalt so they can use their one tool to check their other tool.
Atrenta sells Spyglass-Constraints, which allows you to generate constraints. They claim that they look at
the timing and only generate constraints that matter, so you are not stuck with tens of thousands of
constraints.
Real Intent has at tool to verify false and multi-cycle paths in your timing constraints.
Averant sells a tool for verifying false and multi-cycle paths in your timing constraints.
Apache Design sells a tool called PsiWinder that allows you to do a SPICE simulation of critical paths (using
their NSPICE) with all the power and signal integrity effects included (hence the name PSI).
Nangate sells a tool to create a SPICE netlist of the most critical paths in a design, so the results can be
compared to the static timing analyzer results.
Simucad (Silvaco) sells a tool that will do static timing analysis of a block and then do a SPICE simulation of
short and long paths to create a single timing model of the block, for use during STA of higher level blocks.
SPICE, etc.
Synopsys’ HSPICE must be the worst SPICE simulator on the market. Every single vendor compares
themselves to HSPICE, and they all say they are at least 2X faster. What is interesting is that HSPICE still has
the largest market share. What do the users know that the salesmen don’t? Anyway, doing a SPICE
simulation has two main parts – model evaluation and solving. HSPICE can now split the model evaluation
phase between CPUs and plans are to release a version that can split solving around next March. At a
Synopsys analog panel someone from IBM said that they find multi-treading is inefficient; they said 4 CPUs
will speed things up by only about 1.5X, so they do thousands of smaller simulations independently. A
Synopsys AE I spoke to said that the speedup depends greatly on minimizing network traffic. He said a single
machine with 4 cores will yield about a 3X speedup. I noted that I had heard that multiprocessing starts
running out of gas at about 4 CPUs. He said it depends on the overhead involved in inter-CPU
communication. For different boxes connected on a network, he agreed that 4 were about the limit. For
multiple cores in the same box, he thought you could use 16 or more. Another interesting thing he said is
that once you pass the limit (keep adding more CPUs) you don’t just asymptotically approach some limit, you
actually slow down. Synopsys also sells a tool called Aurora which does device characterization and model
parameter extraction.
Cadence Spectre and Spectre RF are popular tools because it is integrated into Cadences Virtuoso
environment. They can mix SPICE, Spectre and Verilog-A models.
AWR (Applied Wave Research, www.appwave.com) sells a harmonic balance simulator for analog, RF and
system level simulation. It integrates with HSPICE when you need to do transient simulation. Two years ago
they bought Aplac, which had both a harmonic balance and a transient simulator. They now sell both
simulators; the Aplac simulator sells for a higher price than their original simulator.
Mentor sells Eldo, a SPICE simulator. It supports reliability analysis (hot carriers, NBTI), loop stability
analysis, and S-domain and Z-domain generalized transfer functions. Eldo RF is the frequency domain
version for RF design.
Berkeley Design Automation sells a fast SPICE simulator which they say is aimed at really big designs
(>1000 elements, run times >1 day). They have two flavors: analog and RF. They also have a PLL Noise
Analyzer (who doesn’t need that). New for this year is lots of customers (they claim 20 new customers for a
total of 40 engagements).
Legend Design originally sold memory characterization tools but kept bragging about their fast SPICE
simulator (MSIM) built into the tool. They now sell this tool separately and claim it has the best performance
for the price.
Berkeley Design Automation (I missed their booth) sells tools for analog and RF SPICE simulation. They
claim full SPICE accuracy but 5X to 10X faster speeds.
AvoCAD, formerly part of Moscow Research Institute, sells AvoSPICE. It is a transient analysis SPICE
simulator for multiple processors that splits the design between the various processors dynamically
depending on activity level. For analog designs they claim good efficiency, similar to HSPICE, etc. The
amazing claim is that for digital circuitry (where inherently most transistors are inactive most of the time) they
say their tool is about 10,000 time faster than a normal SPICE run, which means you may be able to actually
SPICE an entire ASIC or SOC.
This year I missed Xoomsys, which now has a product to break up SPICE simulations among various
processors for increased speed, but don’t actually have a simulator. They say they can even break up a
grid. Given how everyone who actually has a simulator is working towards a multi-threaded SPICE, this
sounds like a tough business to be in, but if theirs is superior enough it will sell.
Accelicon Technologies Inc. sells SPICE modeling tools. One tool will check a SPICE model versus IV and CV
curves and can also do a basic sanity check on the model without any curves. They can also compare
different model versions to see what has changed. Another tool creates SPICE models from IV and CV
curves. They say they have about 50 customers. They also provide SPICE modeling services.
Sigrity sells a tool that accepts network parameters (S, Z or Y) and produces a SPICE network of passive
components with the same characteristics.
Sandwork Design, Inc. sells tools for SPICE debugging but do not actually sell a simulator. They have a
SPICE linter (boy could I have used that in the past) as well as a tool that lets you examine piecewise linear
waveforms, so you don’t waste time simulating defective inputs. They have put together a debug
environment that is something like Debussy but for analog. You can cross-probe waveforms, netlists
(Cadence or Mentor) and stick diagrams.
SPICE-like simulators
Synopsys continues to sell both the NanoSim tool from Epic and the HSIM tool from Nassda. Synopsys sued
Nassda for infringement concerning HSIM, but interestingly the two tools are so different it is almost
impossible to do a direct apples-to-apples comparison. For example, HSIM tends to be better simulating
memories, NanoSim tends to be better for co-simulation. The two development teams have been integrated
to create a new tool (tentatively named “XA”). The ‘XA Option” will be sold as an add-on to either HSIM or
NanoSim, but yet it is a completely separate simulation engine. At some point Synopsys will decide it is ready
to replace the two existing tools and will financially encourage existing users to switch, but the AE I spoke to
said this is unlikely to happen for at least a year.
Cadence sells UltraSim, a SPICE-like simulator that is integrated into their Virtuoso platform and can natively
read Spectre netlists and models, and can co-simulate with Verilog-XL.
Mentor sells ADiT, a fast SPICE simulator. They claim it is designed specifically for analog/mixed signal
applications.
Magma acquired ACAD so they now have FineSim, a fast SPICE simulator. They say it can mix true SPICE
with table driven SPICE-like simulation, allowing the user to choose speed or accuracy for each part of the
circuit. They also say it is not limited in the number of processors it can run on like HSPICE, and claim it can
run on 2000 processors (that’s quite a claim – one would expect the network overhead to eat up any gains in
processing power). They claim that in one case HSPICE took 32 days to do a simulation (note – HSPICE has
different modes –they didn’t say which one) and FineSim did it in only 12 hours.
Nascentric sells a SPICE-like simulator that they claim is about 10X faster than competing simulators
(because it is current based versus voltage based) and about 1000X faster than SPICE. They advertised
“rocket fast” SPICE and gave away a “pump rocket” – it looked like a rocket propelled grenade but was
tipped with foam – this was probably the most popular giveaway (I preferred the iPod giveaway – sorry).
Legend Design, which sells their MSIM SPICE simulator, has a table-driven SPICE-like simulator in beta, due
out in 3Q07. It is called MSIM Turbo.
Compactors/Expanders
I think Sagantec is still the only independent entry in this field. The sales pitch has changed over the years
(density, speed, create your own libraries, etc.) but for the last few years they’ve sold their tool for process
migration and for Design for Manufacturing (DFM). They have a tool (new?) called SiFix that does minor fixes
to layouts, like end caps, etc. New for this year is a tool to support analog migration. The user adds
constraints to the schematics regarding how the layout needs to look.
Analog/RF and Custom Design
I attended a talk sponsored by Synopsys on analog design. Some issues discussed sounded like digital
issues a decade ago. One speaker noted that for simple digital tests, it is easy to define a pass or fail; the
output is a 0 or a 1. For analog testbenches, it can be much harder to define passing or failing. Also, Verilog-
A can represent circuits but has little support for sophisticated testbench architecture like you would see on
a digital design. One speaker said DFM issues can affect SPICE results by 10%, and named issues like
thermal variation, parametric variation, jitter and phase noise, degradation over time, line edge roughness,
channels that are only 100 atoms wide and gate oxides that are only 3-4 atoms thick.
Cadence Virtuoso, which is integrated with their Spectre and UltraSim simulators, is still the dominant tool in
the analog design arena and other tool vendors strive to be compatible with it. They are proud of their
constraint management technology, where constraints at various phases of the design are automatically
visible at all the other phases. They say this not only helps avoid iterations but also allows IP to be more
easily understood and reused.
At DAC 2006 Jim Solomon, one of the founders of Cadence, said he felt the analog market was being milked
by the dominant players, who offer few new capabilities and inefficient flows kludged together from
acquisitions. He noted that design tools typically have a 7-10 year lifespan but Analog Artist is 15 years old.
He said analog designers don’t complain because they don’t know what they’re missing. I think it could be
more than that.
When I designed logic in the pre-synthesis days, I was proud of the black magic involved; it was like a never-
ending IQ test. When I first heard of logic synthesis, I was skeptical but in the back of my mind I think I was
afraid I was out of a job. Now I write a single line of RTL and get a Booth accelerated Wallace tree multiplier,
which would have taken me months to design. I’m still designing, but at a higher level. I did not make that
transition because I wanted to abandon my comfortable logic design skills, and start doing something where I
would at first be inept. I did it because my project manager DEMANDED I do it, because he thought it was the
only way he could make his schedule. Why isn’t this happening in the analog realm? Given the huge number
of turns some analog designs require, you would think project managers would be jumping on any new
technology. Some analog designers I know claim that by the time you set up the automated tools, you could
do the project by hand. I know a rep from AWR talked about that as a problem in the past. Is that really true?
Anyway, Jim Solomon has been acting on his opinions. He is on the board of Ciranova, which provides Py-
Cells, a free equivalent to Cadence’s P-Cells, and a tool to translate between P-Cells and Py-Cells. They
also have a tool to do analog placement, due out at the end of 2007. The placer accepts the netlist,
constraint file and constraints and produces a variety of placements that maintain constraints like symmetry,
etc.. One unique thing is that it can split up or combine Py-Cells, using either one large transistor or multiple
smaller ganged transistors depending on the layout. Currently they assume hand routing.
Pulsic sells a tool called Unity, which has a hierarchical floorplanner, place and route, ECO routing, and
hierarchical signal integrity analysis in one environment. They say their sweet spot is odd aspect ratios and
limited layers, such as building blocks for memories.
SynCira Corporation sells a tool to do analog place and route. The input is the transistor level netlist, the
layout constraints, design rules, and Pcells. They can also accept yield rules. The tool creates multiple
layouts with different heights and widths and lets the user pick the one that will work best.
Synopsys sells various flavors of their Cosmos tool, which is a design environment that allows schematic
entry, layout and simulation. Their literature emphasizes the advantage of having a single database.
Mentor sells Design Architect, a design environment that allows schematic entry, layout and simulation. They
say blocks can be schematics or models in VHDL, Verilog, SPICE, VHDL-AMS, or Verilog-A. They also sell a
viewer called IC Station; not sure how this is related.
Orora Design Technologies showed two tools. Their Arsyn tool does analog/RF synthesis, going from a
netlist to a sized netlist, based on testbenches and criteria you provide. They can accept requirements via a
GUI or via files, and they have some pre-existing testbenches for measuring performance of common types
of circuits. Their Arana tool extracts analog behavioral models in Verilog-A, VHDL-AMS or Matlab. It uses
different flows for different types of circuits.
Cadence Virtuoso is still that standard tool in this space. For several years now, any vendor that hopes to
survive in analog/RF design has to interface with Virtuoso.
There was a booth for the Interoperable P-Cell Library consortium. Cadence’s P-Cells (parameterized cells
used in analog and RF design) are very old but still proprietary and make it hard for Cadence users to switch
to other vendors. The IPL seeks to define a standard used by many vendors. The original consortium was
AWR, Ciranova, Silicon Canvas (Laker), Silicon Navigator, and Synopsys, and they were quickly joined by
Magma and Virage. It sounds like Ciranova’s Py-Cells may be their alternative to P-Cells.
Silicon Canvas sells Laker, their equivalent to Cadence Virtuoso. Their environment can do design entry,
simulation using various popular simulators, view waveforms and do layout. New for this year are Design For
Manufacturing features and also Design Driven Layout, where it is impossible to make any connectivity
errors. They also have variants for designing flat panel displays, designing test patterns, and for doing ECO
changes in Synopsys, Magma or Cadence databases.
Simucad (Silvaco) sells a suite of tools for analog and RF design. They have schematic entry and simulation
for analog, mixed signal and RF, layout, DRC, LVS and parasitic extraction. They say they are unusual
because they support their own PDK (physical design kit) rather than the foundry.
Analog Rails just announced their analog/RF design tool. It includes schematic entry with physical properties,
automatic routing for analog/RF circuits, a manual router for “correct by construction” design (it aligns, snaps
and repels devices and wires based on DRC rules and connectivity). The databases are tied together; if you
change the schematic the layout automatically changes. They tie to common SPICE simulators but do not
have their own.
Micro Magic sells a tool for design of custom cells. They say it allows cross probing of schematic versus
layout, and automatically enforces DRC rules while you are doing the layout. They say it is also very handy
for debug of DRC/LVS from Calibre.
Anasift sells a tool that accepts a netlist, SPICE models and testbenches, and sizes transistors for optimum
performance and yield.
Agilent sells their popular RF simulation tool (RFDE), but bought competing Golden Gate, which has better
capacity for large simulations of extracted netlists. They currently sell both simulators, and charge more for
the Golden Gate tool. Once they integrate their popular GUI into the Golden Gate tool, they plan to transition
customers to the Golden Gate tool. They also have a PLL simulator due out in August.
Lorentz Solution sells several tools for EM design and analysis. They have a tool for designing inductors,
and another that allows rapid analysis of EM effects during early placement of a design. They have a third
tool to do slotting and metal fill without screwing up your inductors.
OEA sells tools for RF component analysis and also for inductor design and 3D inductor analysis.
Zeland Software sells a tool for designing spiral inductors and transformers.
Helic sells a tool to design inductors. New for this year is the ability to deal with slotting and metal fill. They
also have a tool in beta to do wire bond modeling.
Knowlent sells SPICE testbenches for common analog interfaces. You run your design with their testbench
and they tell you if it is compliant. They support more interfaces than last year, and they now provide a GUI
for the user to create their own testbench.
Evolvable Systems Research Institute Inc. (hard to Google and pointless since the site is in Japanese) sells a
tool for SPICE modeling. The input is a set of IV curves and the output is SPICE model parameters.
Berkeley Design Automation (I missed their booth) sells a tool to analyze noise and jitter in PLLs.
I missed the Kimotion booth this year, and last year I kept going back but the salesman was always booked,
which I took as a good sign. According to their web site, they sell tools to analyze and optimize analog circuits
under environmental and process variations, and it sounds like they are still in beta.
Lynguent sells tools for analog modeling. Some of their folks seem stumped as to how to explain what they
do but their web site helps. They take as input a model written in Verilog-A, Verilog-AMS, VHDL-AMS or
MAST and translate it into their internal xml representation. At this point they can run checks on the model
(for discontinuities, etc.) and provide graphical representations that aid in understanding the model. They
can then output the model in any of the formats they read.
Triad Semiconductors sells a via configurable array for mixed signal (and digital) applications. The array
contains a variety of analog building blocks like op amps, capacitors, resistors, ADCs, DACs, etc. and can be
programmed with only a single via layer. Currently it can hold up to about 150K gate of digital logic. It is
fabricated on Austria Micro Electronics 0.35 micron line and is intended for low to medium volume
applications where the cost of an ASIC can’t be justified. It costs only about $32,500 and takes only about a
month for 10 prototypes; try that with an ASIC.
I missed the Physware booth. They are apparently working on some sort of high speed, high accuracy
analog tool, but it is not due out until 4Q07.
Tanner Research’s inexpensive PC based tools have always been a favorite of smaller analog design
houses who don’t have the cash for Cadence’s tools. Their tool suite includes a schematic capture tool, their
own SPICE simulator and waveform viewer, a layout editor and their own DRC/LVS tool. Their schematic
capture tool can now produce EDIF. Their SPICE simulator now has a multi-threaded engine. The layout
editor now includes a “T-cell builder” for creating their equivalent of P-Cells. They said they will not be
switching to Py-Cells. Their DRC/LVS tool now has antenna checks and now accepts Calibre or Dracula
decks as-is. That last one is a biggie; it is always scary to get a design from a small design house that made
their own rules deck by hand.
Physical Design Planning and Floorplanning
Chip Estimate Corporation sells InCyte, a tool that allows floorplanning and provides estimated sizes.
Normally to do this task, you need to compile basic building blocks for your target library. What is unusual
about this tool is that they provide libraries of building blocks and many IP blocks for various technologies on
their web site (the old VCX web site). They emphasize that their tool facilitates quick “what if” analysis in early
architectural design. They have a free version of the tool for initial estimates and then charge you when you
want more detailed information. New for this year: once you specify the memory sizes you want, the tool has
the ability to output scripts for memory compilers such as those from ARM or Virage.
Atrenta sells a tool called 1 Team Implement. It allows system architects to partition the RTL, come up with
timing and area budgets, etc. It allows RTL coders to understand physical issues without having to learn a
place and route tool. It also has automated floorplanning.
Entasys sells tools for early sizing and power planning. The user inputs a spec in their GUI (like an Excel
spreadsheet) and provides estimated gate count, size and power and they help with the floorplanning. They
can estimate RTL size using a simple estimator or use Synopsys in the background (this is not a synthesis
tool). They emphasize early floorplanning prior to completing RTL. Note their power analysis is based
entirely on user estimates.
Magma sells a tool for early design planning that is targeted at their tools. I believe it uses the less CPU
intensive routing algorithms so that most of the routing is close to what you will eventually get. That is one
thing the independent floorplanning companies try to ignore; if you use two different place and route tools,
you might get two entirely different delays for the same top level net.
Cadence sells First Encounter, a design planning and floorplanning tool that is the front end of their SOC
Encounter tool suite.
Synopsys sells Jupiter, a design planning tool targeted at their place and route tools.
Javelin Design Automation sells a prototyping tool. It accepts System C, RTL, gates or black boxes and
allows high level partitioning, congestion and timing analysis. It allows for iterative refinement as the design
progresses. It outputs synthesis constraints as well as floorplans for First Encounter or Jupiter with LEF/DEF
or PDEF/SPEF. They say they are in stealth mode so the name is secret (they’ll tell me what it does but THE
NAME is secret!?! Is this a Dilbert episode or what?).
Logic Synthesis and Optimization
Synopsys Design Compiler still dominates this realm, and claims to have the best quality of results. The
many free building blocks they deliver as DesignWare also provide an advantage because they make pre-
existing code less transportable, but some vendors are providing their own equivalents. Their latest versions
support “topographical technology”, which means the synthesis tool has a rough idea about placement and
uses that to estimate net capacitance, rather than starting with wire loads. This internal place and route
estimation occurs without any user intervention. I would assume the estimates work best with Synopsys place
and route tools.
FTL Systems sells a tool that they claim will do behavioral or RTL level or analog/mixed signal synthesis. I
didn’t see a demo; I’d be interested how you can mix those.
Incentia sells a logic synthesis and optimization tool that is DFT aware and they claim is better at low power
optimization than standard tools. They claim the low VT cells it inserts can improve power by 10-15%, even if
another tool has already attempted optimization for low power.
Nangate sells a tool that analyzes timing in a design and actually creates new standard cells to benefit that
particular design. This is sometimes done by combining cells that appear in the critical path and sometimes
by creating cells with new, more optimal drive strengths.
Library Technologies sells a tool that analyzes timing and creates new cells that would benefit the design.
Last year it was being sold as a way to close timing, but this year it is being advertised more as a way to
reduce power (it will do both, but the change in sales pitch says a lot about which way the wind is blowing).
Prolific (www.prolificinc.com) sells a tool to optimize timing. They do resizing of cells, swap cells and can
create new macros to minimize routing. They claim it works better at this than the optimization engines in
commercial synthesis tools. It uses Primetime so there are no arguments about whether it still meets timing.
Physical Synthesis
Magma claims that once the setup files have been verified, their tools can take a change in RTL to a new
GDSII in only two days. They say they are ready for 45 nm, including statistical timing analysis and yield
issues, and were proud they were part of the TSMC reference flow.
Incentia sells a physical synthesis tool based on their logic design tool. They say it simultaneously optimizes
for timing, area, power, signal integrity, congestion and DFT.
Atoptech was in stealth mode and I didn’t see them at DAC. Based on the advertised job openings they are
creating some sort of physical synthesis tool.
Place and Route
Sierra Design Automation (www.sierra-da.com) sells place and route software. They say their place and
route tool is variability driven and is natively multi-corner/multi-mode and hence better than competing tools
that have tried to add this capability to existing code. They say their router is aimed at 45 nm DFM issues. It
is “litho driven”; it works directly with Calibre and fixes errors automatically. If that really works it will make a
lot of place and route folks very happy. They were purchased by Mentor just after DAC, I assume in part
because they were a whole lot cheaper than Magma.
Cadence sells NanoRoute as part of the SOC Encounter suite. New for this year is “superthreading” – a
combination of multithreading and parallel processing that they say allows the tool to route millions of nets
per hour on inexpensive 32 bit compute farms.
Synopsys IC Compiler is their place and route tool. They emphasize tight integration with their Primetime tool,
which is the most common signoff timing tool, so there is less chance that the P&R tool will think timing is fine
but the signoff tool says it fails. They also emphasize faster closure since it works to optimize for yield and
testability.
Athena Design Automation sells tools that claim to make your existing place and route and analysis tools
more effective. Their tools provides a single front end for multiprocessor runs. They do not replace LSF like
Runtime Design Automation; they provide a shell atop that (or Sun’s equivalent to LSF). One of their tools
simultaneously optimizes your placement and routing over multiple design corners.
InternetCAD.com sells their entire suite of tools for $25K per year. For that you get a floorplanner, a timing
driven standard cell and gate array placer, and gridded and gridless global and detailed routers. Capacity is
up to about 500K placeable objects. They are used to route digital portions of predominantly analog
designs, by Micron for DRAM design, and they say their tool is buried in some of Intel’s home-brew software.
Tuscany Design was in stealth mode last year and this year was so jammed I couldn’t talk to anyone. They
sell a tool for structured initial placement that they say is 2X the performance of Cadence or Magma, and I
believe they still do not have a router (of course routing is where you find out the mistakes you made in
placement, but it’s still hard to sell just a placer). They also have tool to close timing for top level routes.
Lizotech has a lithography aware router (they have no placer). They claim their router creates about 30%
fewer vias than Astro with about 2% better line length. They introduced their tool at DAC 2006 but at DAC
2007 it is still in beta. Are they hoping someone will buy them?
Pyxis Technology (I missed their booth) sells a router that is yield aware and better able to handle the many
new rules for 65 nm and 45 nm design.
FTL Systems says they sell a tool that does place and route, optimization and analysis.
Azuro sells a tool for clock tree synthesis. Last year they seemed to be selling it as a low power solution, but
this year they emphasize the mixture of low power, low skew and small area. The tool optimizes for multiple
modes and corners at once and is aware of On Chip Variation (OCV). The tool analyzes activity, either
based on VCD vectors or using vectorless analysis, and inserts gating. They claim 20% less power than
clock gating done at an RTL level. They say their tool is used by TI, Broadcom and NVIDIA. I would think that
for skew, a hybrid mesh like Cadence uses is bound to be better, so this is probably best for designs where
power is paramount.
Teklatech is a Danish company that sells a tool for clock distribution. They say it is robust to variability
because they use a grid structure. They do not use a mesh; there are no outputs tied together. There will
probably be some skew in their grid, which they say you can use if the clock grid is going opposite the
direction of a pipeline. I’m not sure what happens if your design doesn’t really have a pipeline.
OEA sells a tool for design and analysis of clock networks and another tool for design and analysis of bus
structures on-chip.
Library Technologies sells a tool for optimizing clock networks. Rather than moving buffer cells and changing
routes, it analyzes the network and then actually creates new cells with the exact correct drive strength to
minimize skew and power.
I missed Manhattan Routing, Inc. (www.mri-nyc.com), which sells a tool to fix “the last 100 paths”. It keeps
track of timing, physical and logical information and allows the user to quickly fix problems. They emphasize
that they use your signoff timing tool rather than one inside their tool, so there are no arguments at the end
about whether it passes timing.
Supply Drop, Noise Analysis, Thermal Analysis, etc.
Apache Design Solutions had a demo about how Cisco used their tool for power, voltage and jitter analysis
(jitter is a hard one). They did a 1 million gate design and it required about 30 GB of memory. Interestingly
the analysis showed that the bypass caps did very little because of inductance. Apache’s RedHawk tool
performs dynamic power analysis and closure and includes the effect of simultaneous switching, decoupling
capacitors, and on-chip and package inductance. One of the things Apache emphasized last year was that
power, thermal and electrical effects are interrelated. You can use nominal electrical conditions to calculate
power numbers, and those yield thermal numbers. But those thermal numbers imply new electrical
parameters, which imply new power numbers, which imply new thermal numbers – ugh! This year they have
their Sahara-PTE tool to integrate all three types of analysis and close that loop quickly. Apache also sells a
tool called Sentinel that includes package and board effects when analyzing power integrity, and can also
analyze Electromagnetic Interference (EMI) and simultaneous switching effects on outputs.
Sequence Design sells a tool called CoolTime that allows simultaneous analysis of voltage drop, power,
timing, electromigration and signal integrity. It includes the effect of package and decoupling capacitors.
They do their own cell characterization for power characteristics and they use their Columbus parasitic
extraction tool internal to this tool. The analysis is dynamic and can handle memories. New for this year is
analysis of simultaneous switching noise. They have another tool called CoolPower that tries to fix power
distribution problems with decoupling capacitors, etc. and can also insert power gating.
Cadence sells CeltIC, which is integrated into their SOC Encounter suite. They say it accurately calculates
the impact of crosstalk and IR drop on both delay and functionality. The input is library models, SPEF from
an extraction tool like their Fire and Ice tool, and possibly IR drop information from a tool like their
VoltageStorm. Their VoltageStorm tool can analyze supply drop either statically (estimates without vectors)
or dynamically using VCD from simulation. They sell another tool called ElectronStorm just for
electromigration analysis. They sell yet another tool called PacifIC for static (no simulation) noise analysis.
Synopsys Primetime SI is an extension to their industry-leading Primetime tool that adds signal integrity
analysis capability. It can handle both delay issues and actual glitches that affect function. It calculates the
timing windows where signals are able to switch and can do vectorless operation this way. Synopsys has a
new tool called Primetime PX which allows full chip concurrent timing, signal integrity, and power analysis. It
can use VCD or SAIF to get real switching activity. Synopsys PrimeRail allows static and dynamic analysis of
power networks. It can handle multi-mode analysis of multiple voltage islands with power gating. It is
somehow tied to the new Primetime PX but I’m not sure how. They also have a new tool called NanoTime that
sounds like an improved version of Pathmill. It is a SPICE-like transistor level static timing analyzer that they
claim is within 5% of HSPICE and can handle signal integrity effects.
Magma sells two tools for power and noise analysis but they seem to overlap a bit. One analyzes supply
drops, calculates extra gate delays associated with supply drops, and checks for electromigration. The other
does static timing analysis and includes the effect of supply drops and crosstalk induced delay and glitches.
Sigrity sells signal integrity tools (no surprise there). Their tools analyze power and signal integrity in chips,
packages and boards, and also create non-symmetric SPICE models based on networks from field solvers to
allow faster analysis. They also have a tool that helps choose location and size of bypass capacitors, and
provides a cost/performance graph to the user for various capacitors.
Incentia sells a tool for signal integrity that is built on their Static Timing Analysis tool. They say they use a
proprietary current based model for better accuracy, and that their tool uses path dependent delays for
better crosstalk analysis accuracy.
CLK Design Automation had a booth but I missed it. They have tools for static timing analysis and also signal
integrity analysis that they say are faster for two reasons. First, they are multithreaded with very low
overhead for adding additional processors. Second, they say their tools are incremental, so while iterating to
fix bugs, they analyze only the changes to the design.
OEA International sells three tools for power buses. One helps with planning, one creates the grid used by
the logic and one makes the ring for the I/O.
Ansoft sells tools for analog/RF design, simulation and analysis. They have tools for 2D and 3D signal and
power analysis of packages, boards, and on-chip passive components. They have two highly accurate
extraction tools and also a simulator.
Agilent says they have EM extraction and convolutional transient simulation built into their ADS tool, so it is
capable of predicting things like bit error rates.
Coupling Wave Solutions (www.cwseda.com) is a French company that sells a signal integrity tool for mixed
signal and RF design. They have a tool that examines manufacturing data to understand how to characterize
cells for signal integrity, a second tool that will analyze all the cells in a library, and a third tool for IP vendors
to provide information without giving away exactly what is in the IP. Their analysis tool then extracts all the
relevant information from all the propagation paths, including substrate, interconnect and package
parasitics. Noise can be monitored at any point in the system.
Applied Simulation Technology (www.apsimtech.com) sells high frequency noise analysis software
(extraction, modeling and simulation) for boards, packages and (they say) chips. Their tool can plug into
HSPICE. They claim they can SPICE the entire power/ground network of an ASIC.
Micrologic Design Automation sells a tool that does a vectorless analysis of IR drop, electromigration and
self-heating.
Mentor sells HyperLynx, a suite of PCB tools for analysis of signal integrity, crosstalk and EMC. Their Quiet
Expert tool sounds similar – not sure what the difference is.
Optem Engineering shared a booth with Tanner and I missed them. They sell tools for 2D and 3D EM and
signal integrity analysis of packages, boards, connectors and (unusual) cables. They also have a tool for
chips; I’m not sure of the capacity.
Gradient Design (www.gradient-da.com) sells a tool for thermal simulation. The input is LEF/DEF, package
information, and power information from PrimePower or VoltageStorm. The output is a thermal map of the
device. They emphasize that their simulation is much more accurate than competitors, and say they can
show the temperature of a single finger of a power transistor. They say this kind of accuracy is necessary
with today’s designs.
Design for Manufacturing (DFM) and Yield Related Tools
I attended a Synopsys talk on analog design. One speaker said they used HSPICE to resize transistors in a
NAND gate. They wound up with a 5% increase in delay and a 1% increase in area. In return they got 35%
less standard deviation over process and also 37% less leakage. It shows what going for speed and area at
all cost can actually cost. One speaker said DFM issues can affect SPICE results by 10%, and named issues
like thermal variation, parametric variation, jitter and phase noise, degradation over time, line edge
roughness, channels that are only 100 atoms wide and gate oxides that are only 3-4 atoms thick.
Last year a few foundries (like TSMC, UMC and IBM/Chartered/Samsung) finally started releasing yield
information for tools to use to predict the yield of a design, although each foundry was using their own
encrypted format. Some tools read this for one or another foundry, some use real data from other sources
(particularly PDF Solutions), and some require the user to guess about yield information.
Ponte Solutions sells tools for yield analysis by analyzing process variability. They say they are the only
vendor that accepts encrypted data from all the major foundries that provide it. Their tool allows the user to
customize DFM rules if desired. They are working on CMP modeling (using their own model) and lithographic
modeling, teamed with Blaze DFM.
PDF Solutions sells tools for yield improvement. One tool creates test structures to measure failure rates.
They call them CV structures but that is apparently their trademarked name, not Capacitance-Voltage. Their
tools help you modify your cell layouts to improve yield, and they have tools for both digital and analog
support. Their tools work with Cadence and Magma, and after physical verification they can do yield based
signoff in the Magma flow. They also provide services to optimize a design for yield improvement.
Nanovata Design Automation sells a tool for interconnect optimization. They say it can simultaneously
improve timing, signal integrity and yield. The yield improvement is done by reducing critical areas and
adding redundant vias, but the yield calculations are based on user input, not direct real-world data from a
fab, PDF, etc.
Anchor Semiconductor sells a suite of tools for DFM. Their tools do analysis using a pattern-centric model
based algorithm (which they contrast to Mentor and Synopsys), Verification of OPC and RET, and
lithography modeling. New for this year is quick classification of design induced defects, pattern based OPC,
and the ability to customize the flow for specific layers.
Nannor sells a tool called Acuma for analysis and correction of yield issues. The input is GDSII and yield
models from Prediction Software (not at DAC). It identifies problems and fixes them, but they claim it is more
sophisticated than a simple compactor/expander. New for this year is the ability to do lithographic simulation,
which they apparently acquired by partnering with a company called Lithograph Simulation (not at DAC).
They say their nomenclaturally confusing competitor Nanno Solutions was bought by someone; they weren’t
at DAC, anyway, and their web page is way out of date.
Mentor sells Calibre LFD (litho-friendly design) to analyze and design for yield issues and automatically
correct most errors. It also produces a “Design Variability Index” that allows users to decide which design of
several options is the most immune to process variation. They also sell Calibre YieldAnalyzer and Calibre
YieldEnhancer – I’m not sure how these relate to LFD. They also sell three tools for Optical Proximity
Correction (OPC) and Phase Shift Mask (PSM) verification; I’m not sue how they differ.
Synopsys sells PrimeYield for yield analysis and enhancement. It can both predict and correct yield issues.
Cadence sells a tool for yield improvement called Chip Optimizer. It is integrated into both the Virtuoso
(analog) and Encounter (digital) tool suites. They also sell a tool supporting Resolution Enhancement
Techniques (RET).
Clear Shape Technologies sells two tools for improving yield. They take GDSII and analyze it for lithographic
hot spots using model based rule checks.
CommandCAD had a booth which I missed. They sell Design for Yield tools that have a pattern matcher – it
finds patterns in your layout that are close to patterns in their library. They can also do binning of error
markers so you see how many problems occur in areas with similar topologies.
Solido Design Automation sells a tool for transistor level statistical design and verification for improved yield
of analog, memory and small digital designs where there is significant On Chip Variation. They say their tool
is different from Monte Carlo analysis and is part of a more predictable design flow. It highlights yield problem
areas and suggests changes.
Anasift sells a tool for analog Design For Manufacturing. You input your SPICE netlist and SPICE models,
and it simulates for sensitivity to process variation and sizes transistors to yield for the biggest range of
conditions.
This year I missed the booth for MunEDA (ChipMD here in the states), which sells tools for analyzing and
improving the yield of analog circuits.
Blaze DFM sells an interesting tool that analyzes your design and provides detailed instructions to the OPC
software. The tool understands timing and can slightly shorten or lengthen the channel of transistors to
provide greater setup or hold time margin. It also lengthens channels slightly to decrease static leakage.
They claim there is no need to rerun timing because this is only done on non-critical elements.
Magma sells a tool for feeding yield information back into your design. It accepts both systematic and
random yield information and can use that to redesign cells or create new routing rules. Magma bought the
Knights failure analysis software and they see themselves in a unique position to provide feedback like this.
FTL Systems sells a tool for hardening a design against single event upset failures.
I missed the Takumi Technology booth. According to their web site, they sell tools to improve yield, and they
believe they have the only tool to automatically fix hot spots. Their tools also automatically categorize hot
spots and rate them in terms of severity.
DRC/ERC/LVS
Mentor’s Calibre tool is very widely used and is one of the chief sources of revenue for this company. They
use a “hyperscaling” architecture, where a few processors queue up data for the rest that do the work, and
claim to effectively use up to 100 processors.
Hercules is the Synopsys tool for DRC and LVS and is widely supported by foundries.
Magma claims that their Quartz DRC/LVS tool is better than competing tools at using large numbers of
processors. Normally, if you try to use too many processors to do a job, the overhead of the network
communications outweighs the gain from additional processing, and at some point dividing the job between
more processors can actually slow it down. Magma claims this tool does not suffer from this difficulty and with
enough processors it can do any DRC job in 2 hours or less. If that’s really true it will make a lot of back end
folks happy.
Cadence sells a tool called Assura for DRC and LVS. Some fabs now allow it for signoff. They claim that their
use of hierarchical processing speeds the tool. They have a separate tool called Diva that runs within their
Virtuoso analog design environment.
Micrologic Design Automation is working on a tool (due out Oct. 07) that will automatically fix LVS problems
while the user watches. It is supposed to plug into Virtuoso and work with LVS output from Calibre, Hercules
and Cadence. They are working on an OpenAccess interface as well.
Parasitic Extraction
Magma sells QuickCap, the standard field solver in this area. Note that “quick” is only true relative to the
original (and more accurate) Raphael solver from Synopsys. This tool is still very slow and there is no way
you can use it on more than a few nets at a time. Their new version allows foundries to encrypt process
information and also allows the tool to run on multiple processors. Magma also sells Quartz RC, a rule based
RC extraction tool, which they say is tightly integrated with their implementation tools.
Sequence Design sells Columbus, a high accuracy extraction tool that uses a library created using a field
solver. They say it has statistically accurate corners so it reduces pessimism. They say some customers
have reported 30% better margin.
OEA sells a 3D field solver tool for creating RCLK SPICE decks of selected nets, trees or critical paths.
Mentor sells several flavors of Calibre for RC and L extraction. They say it is tightly integrated with their DRC
and LVS tools.
Synopsys sells Star-RCXT, a widely accepted RLC extraction tool. They emphasize that more than 99% of
the nets they extract are within 5% of results from Raphael.
Cadence sells QRC, a 3D extraction tool integrated into their SOC Encounter tool suite. They claim the tool
offers all the capabilities of their older Assura tool and the Fire and Ice tool they got when they acquired
Simplex.
EDXACT sells an interesting tool. Most extraction tools create DSPF (detailed standard parasitic format) files
which are far too large to use. These are turned into RSPF (reduced …) which are a manageable size but
less accurate. EDXACT sells a tool for reducing file size but maintaining accuracy to whatever level of
accuracy the user desires. They can also output SPEF, SPICE or Spectre format files. New for this year is
better integration into a Cadence environment. They also sell a tool that does an initial sanity checks on
parasitic files (power shorts and opens, etc.) before you waste a lot of time on them.
Lorentz Solution sells a tool for 3D EM analysis and is designed to integrate into Spectre RF.
Pextra Corp. sells a 3D field solver that they say is faster than Quickcap but within 1% of the accuracy of
Quickcap and Raphael. They say it is architected to do multiple corners in only a little more time than doing a
single corner. They also sell some sort of mixed 2D/3D solver for better speed but I didn’t get any details.
Mask Related Tools
Talking to vendors is sounds like OASIS is really not taking off as a replacement for GDSII. TSMC now
accepts it so different companies are supporting the format, but the transition is slow. One OASIS supporter
said the TSMC now regularly gets GDSII files in the 500GB to 1 TB range and they want OASIS to bring this
down to a reasonable size. Several other vendors said this is really rare; tens of GB is the biggest GDS files
they normally see. OASIS achieves compaction by searching for repetitive patterns and creating new cells
for these patterns and hence new levels of hierarchy. Technically this process is supposed to be optional
although some vendors always do it. I have heard some concern over the new hierarchy levels which don’t
correspond with anything in the design, but one vendor said they disappear when you write out any other
database from OASIS so they aren’t a problem.
Lavis sells a high performance viewer for GDSII, LEF, OASIS, MEBES, etc. They said the OASIS portion is
selling only in Japan and Taiwan. Their tool interfaces to DRC/LVS tools from Mentor, Synopsys, Cadence
and Magma, as well as the lithography simulator from Brion.
CAD Science sells ICEView and ICEEdit, a viewer and editor for GDSII and OASIS. They also sell a tool
called ICARuS which does DRC and ROPC checks on mask data. They noted that on a 32 bit machine,
OASIS will use 28 bit numbers, which is not enough to represent some long runs on large chips, so you may
need to run it on a 64 bit machine.
Xyalis sells various mask related tools, including GDSII viewers, frame generation software, multi-chip project
tools, and a GDSII merge tool, but their booth emphasized their metal fill tool. New for this year are
density/roughness parameters. Actually they have three metal fill tools (a model-based tool, a rule-based
tool, and a hybrid tool) but their web site only advertises the hybrid one. They said they support OASIS but
have only one customer for it (ST).
Laflin Limited was selling HOTSCOPE, which was created at Dai Nippon Printing. This is a high performance
data viewer for GDSII, OASIS, MEDES and other formats. They say they can open a 1 terabyte MEBES file
using only 2 GB of memory.
Micro Magic has a GDSII viewer that they claim is the fastest in the world. It is free until DAC 2008, along with
the interface to Calibre.
Artwork Conversion (www.artwork.com – got their domain name early!) sells fast viewers and plotters for
GDSII and OASIS. They say their plotter software is cheaper than support for HyperPlot. They also have a
tool that plugs into a Cadence environment to provide a 3D view of packages, including stacked die and
MCM packages.
Saratoga Design Systems sells a tool that compacts GDSII by finding repetitive patterns. They claim
compaction is about 2X but they’ve seen cases where it is much higher. They claim to have picked up a
number of customers since last year.
Pinebush (represented by the Shearwater Group at DAC) sells a tool for manipulation of GDSII or OASIS.
They also have an inexpensive layout viewer. They say that some customers are switching to PDF for layout
documentation, and they have a PDF viewer that can handle an entire chip. They also sell the very common
HyperPlot plotting software.
Mentor sells a flavor of Calibre for fast viewing of designs that will also do some editing.
Synopsys sells three tools for OPC correction. Progen helps users create models that fit empirical data, while
Prospector helps with visualization and analysis. Proteus is the tool that actually processes data, and can be
run in parallel on a large number of nodes.
Blaze DFM sells an intelligent metal fill tool. It works to ensure that fill does not affect the timing or power of
the design.
Invarium had a booth but I missed it. They sell a tool for “Process and Proximity Correction (PPC)” that
“replaces legacy OPC tools”. Guess I need to learn yet another acronym. They emphasize that you may
want to do different things to a mask in very similar situations in the layout. Their tool separately simulates
mask, resist contour and etch contour, so they claim they are better able to precisely correct for each layout
situation.
Brion had a booth but I missed it. They sell a tool for doing Optical Proximity Correction (OPC) and checking
OPC results.
FPGAs
Synplicity is probably the leading FPGA synthesis provider, in part because they limit the number of details
the designer has to deal with. In addition to basic synthesis, they also have a physical synthesis tool that
helps control timing by providing placement. They have a tool called Identify that facilitates debug of FPGAs
using the JTAG port. It is driven by RTL and annotates results onto the RTL, so it looks like an RTL
simulation but is actually doing hardware testing. If the part only fails in the real system, there is also the
ability to capture stimulus up to a failure (or an assertion firing) so that the designer can reproduce a real-
world failure in simulation.
Mentor sells two different sets of FPGA synthesis tools, Leonardo, which it calls (well-proven, mature” and
Precision, which has a physical synthesis option.
National Instruments (www.ni.com) sells LabVIEW, which also does digital design. The code is entered
graphically; it creates VHDL internally and uses Xilinx tools to design hardware to implement that function.
Another tool turns graphical input into C code for common processors. They were proud that their software is
used in Lego MINDSTORM.
I missed the Temento booth. They sell tools for FPGA debug, and allow a designer to embed logic analyzers,
glitch detectors, multi-condition triggers, and a variety of other temporary hardware to debug the design.
Packaging and Boards
I saw the Cadence demo on their MCM/SIP tool. They said SIP (System In Package) is being driven by 1.
mixing technology in a system 2. not producing enough parts to justify an ASIC, and 3. not having enough
time to do an ASIC. They said one problem is that there are so many options like side-by-side versus
stacked, wire bond versus flip chip, etc. that it can take months to define them all enough to do tradeoffs.
They said that many designers use an Excel spreadsheet for connectivity information which precludes doing
LVS. Their tools include: 1. System Connectivity Manager – this is the master netlist for LVS 2. SIP Layout
and 3. SIP SI – extraction and characterization using a 3D RLC tool. The Connectivity Manager can read in
Verilog ports from various models and tables from the user. It won’t read VHDL as-is (requires user
processing). It supports hierarchy (a die stack can be a hierarchical entity, for example).
Cadence sells both Allegro and OrCAD for PCB design. The Allegro tool is more the high end tool. EMA
Design Automation represents Cadence and sells the venerable OrCAD tools as well as their other board
level tools. New for this year is use of open GL for graphics, as well as more capabilities from the mouse pull-
downs. They are moving towards full 3D modeling of the board within Allegro.
Mentor sells a suite of tools for board design, including Board Architect (schematic entry and PCB layout),
Design Architect (hierarchical, can mix PCB and ASIC), TAU (timing analysis), HyperLynx and Quite Expert
(signal integrity), and Expedition (PCB router).
Rio Design Automation sells a tool for chip/package co-design. Package design starts with just an estimate
of size and pin count, then a Verilog netlist, then LEF/DEF. It does route planning and finds potential
problems. It is not a package design tool; you still need to do detailed design there; this tool does route
planning for wire bond or flip chip packages. The output is a spreadsheet, DEF and Verilog. If nets have
different names on different chips and MCM routes it keeps all that straight internally. It currently cannot
handle stacked die, only side by side. SIP support is due out in December.
Sigrity sells signal integrity tools (no surprise there). Their tools analyze power and signal integrity in chips,
packages and boards, and also create non-symmetric SPICE models based on networks from field solvers to
allow faster analysis. They also have a tool that helps choose location and size of bypass capacitors, and
provides a cost/performance graph to the user for various capacitors. They have another tool that facilitates
co-design of the chip IO and the package.
Optimal Corp (www.optimalcorp.com) sells tools for EM and thermal modeling of packages and boards. They
also have a tool for power grid design. Their goal is concurrent design of chip package and board. Cadence
OEMs their tools for their SIP flow.
Optem Engineering shared a booth with Tanner and I missed them. They sell tools for 2D and 3D EM and
signal integrity analysis of packages, boards, connectors and (unusual) cables. They also have a tool for
chips; I’m not sure of the capacity.
Zeland Software sells several tools for EM analysis of components, leads, BGA packages, power/ground
planes, PCBs, SIP, etc. Their tools hook to tools from Cadence and AWR. They also sell tools for design of
coplanar and coaxial filters.
OEA sells tools for parasitic extraction of package traces with automatic SPICE sub-circuit generation, and
for 3D inductance simulation of packages.
NEC sells a tool for package optimization, and also board design services.
Quik-Pak is a services company that does quick-turn packaging prototypes, and says they can provide initial
prototypes in less than 24 hours.
MyCAD sells inexpensive PC based design tools for PC boards and is often used by universities. New for this
year is support for ICs and MEMS.
Test
Mentor has a complete line of test tools. DFT Advisor does testability analysis and inserts test hardware.
FastScan does ATPG for full-scan designs and FlexTest does it for partial-scan or non-scan designs.
TestKompress compresses vectors by distributing them to many short scan chains and then combining
results. MacroTest creates scan based (non BIST) tests for small memories. MBISTArchitect adds Built-In-
Self-Test (BIST) to embedded memories and supports Built-In-Self-Repair using redundant columns and
rows. BSD Architect inserts boundary scan around I/O. Yield Assist helps isolate failures based on failing
patterns.
Synopsys DFT Compiler is the portion of their synthesis tool that inserts testability. Tetramax is the tool that
checks and in some cases fixes testability, generates full scan or partial scan ATG vectors, and simulates
the vectors with a unit delay simulator. It also allows at-speed testing and IDDQ testing, and can help with
fault isolation. DFT Max compresses test vectors for both stuck-at and at-speed testing by distributing them
to many short scan chains simultaneously and then creating a single result from all those chains. LBIST
Architect inserts logic BIST, and has a patented algorithm for inserting new test points. BSD Compiler inserts
boundary scan, checks it and creates patterns.
Atrenta says they can now predict ATPG coverage numbers at RTL and they are working on speed
coverage. Their Spyglass tool is designed to pinpoint testability issues before synthesis, so iterations are
saved.
LogicVision sells various test tools based on Built-In-Self-Test, where the circuitry generates pseudo-random
inputs and the outputs are compressed and compared to the correct answer. Their memory BIST supports
Built-In-Self-Repair using either fuses or registers. They also support logic BIST and their tool helps with
insertion of extra test points. They also have tools to support boundary scan and SERDES testing, as well as
pattern compression. I know some people feel their products are point tools with delusions of grandeur; they
are so invasive in the design flow that they aren’t worth it. They would probably respond that test involves
many steps in the design, and I know the AE claimed the interface had gotten easier in the latest release.
New for this year is the ability to use a burst of scan data to mimic the power used in normal function, so you
get proper speed binning. They’ve also got a neat product that (if I understood correctly) allows you to
connect the JTAG port of a chip to the USB port of a Linux PC and test the part that way.
Syntest continues to be a great looking girl with no date for the prom. It looked like Cadence (or maybe
Magma) might buy them but both have developed their own test tools. They have a complete suite of tools
including testability checks, scan synthesis, ATPG, fault grading, memory and logic BIST and boundary scan
synthesis. Their fault simulator accepts SDF (most fault simulators do not) and is many times faster than
Verifault, in part because they use their own primitives (you translate the Verilog library). That tool is
apparently selling OK. They have bundled up all the rest and sell the suite at a single affordable price. I have
dealt with this company and they are very engineering oriented; the technology is good but sales literature
and manuals have been awfully detailed in the past, though they seem to be getting better.
Genesys Testware (www.genesystest.com) sells tools for memory test. They now have a GUI that enforces a
flow for BIST insertion (took a page from Logicvision’s playbook perhaps). In addition to Built-In-Self-Test
(including memory retention testing) and Built-In-Self-Repair of soft errors (no fuses needed), they also
support embedded boundary scan. They can also create boundary scan around individual blocks to that
testing can be done hierarchically. They support Synopsys, Cadence and Magma. Insertion is during
synthesis; there are no RTL changes. Input can be RTL or gates, output is always gates.
Intellitech sells software and IP for PCB level test using boundary scan and JTAG. They sell controllers that
test memories, test connections between chips, and kick off logic BIST on a board. These controllers also
allow upgrades in the field. They can also test at-speed SERDES/DDR. They are currently targeted at
FPGAs (Xilinx) and may move to ASICs later. Another interesting product is a box that hooks an IEEE 1149.1
interface to a network, so that you can test boards from the computer on your desk.
TSSI (Test Systems Strategies, Inc) has for years sold software to translate test vectors from generic formats
(like WGL) to the correct format for specific tester hardware. They were purchased by Credence, a specific
tester company, and that made many other test companies uncomfortable having them be the front end for
their hardware. Two years ago Credence spun them off. They say they have updated the virtual tester used
to debug the test program before parts arrive.
Advantest was at DAC again selling their unique CertiMAX tester that does not use cycle-based data. They
showed this at a few DACs, gave up at the 2005 DAC and the salesman explained why the idea failed, but
then they were back last year and this year. Most testers (including most of the ones Advantest sells) require
that you define a cycle and specify when within that cycle each input changes and each output is checked.
This tester accepts VCD directly. Inputs are changed at the same time as the VCD, outputs are checked
whenever a transition occurred in the VCD, and they can filter out glitches as defined by the customer. This
type of tester tends to be expensive and slower than normal production testers. They are sold for
engineering debug, where the engineer can generate VCD from a simulation and immediately test it. One
advantage of this scheme is that it is easy to handle multiple clocks, even if they are not simple multiples of
each other or even if they are completely asynchronous. Two disadvantages are: 1) you must bring up your
test both on this tester and your production tester and 2) there is no way to generate schmoo plots.
National Instrument sells software and hardware to turn a PC into a basic tester. Capabilities are obviously
more limited that a production tester and cost is a tiny fraction of what production testers cost.
DeFacTo Technologies (www.defactotech.com) licenses some Syntest technology for RTL level scan
simulation. Simulation a whole SOC doing scan testing for many thousands of clocks is very time consuming.
They plan to do it at RTL level. I’m not sure how they address scan chain reordering by place and route
tools. They were in DAC 2006 but the tool is not due out till 4Q07.
Magma bought Knights, which makes failure analysis software. This software takes the netlist, layout and
vectors and helps an FA engineer determine the cause of a failure. They also have a yield management tool
to try to correlate failures to yield detractors. Magma hopes to strengthen the ties between failure analysis
and design, so that FA data can be fed back into a design flow, and also the testing can be done so that it
the parts of the chip that are most likely to fail are tested first.
Design Collaboration, Design Management and Similar Tools
Mentor sells two tools (HDL Designer and HDL Detective) that supposedly help designers with legacy code.
They do things like a connectivity analysis (what’s not connected), design visualization (either graphically or
in a spreadsheet format), and code quality assessment.
Enovia bought Matrix One, which had bought Synchronicity. Synchronicity has Design Sync, a web based
version control system that allows multi-site access to files with advanced branch and automated merge
capability. They also sell IP Gear, which supports a single database for IP distribution. It now seems to be
aimed more at reuse of IP within a company, rather than setting up competitors to Design and Reuse. They
also have a tool for project management that allows issue tracking and management.
IC Manage had a booth but I missed it this year. They have a design management tool that as of last year
they said was up to 100 times faster than Synchronicity, required less scripting, was multi-site, and cheaper
than Synchronicity per ACTIVE user (not sure what that meant).
Design and Reuse, by far the largest IP website, sells a tool similar to IP Gear, designed for firms to set up
an internal design reuse site.
KETI (Korean Electronics Technology Institute) had a booth that displayed a tool for web based IP reuse.
The FSA (Fabless Semiconductor Association) had a booth where they talked about a tool for evaluating the
risk of hard IP. I didn’t see it but I’d be interested to see if an association would really take business from one
IP vendor and send it to another.
Cliosoft sells a design management tool called SOS. They were originally tied to Cadence but have
supported Mentor and Silicon Canvas (Laker) tools for several years. Last year they added access controls
and authentication, and the concept of “composite objects” – sets of files that are always saved and restored
together. This year they have added bug tracking and the ability to have a reference project.
Mentor sells tools called TeamPCB and Xtreme Design, which allow multiple designers to work on the same
PCB at once.
Platform Computing sells LSF, used to distribute batch jobs among a group of computers. New is the
capability to cluster hosts and to dynamically move hosts from one cluster to another. They say they can now
handle tens of thousands of CPUs on a single network.
Aldec sells a server farm manager. They say it is better specialized for simulation tasks than general
purpose tools like LSF.
Runtime Design Automation (www.rtda.com) sells a tool to automate your design flow. One application is
where you have a few experienced designers (say, in San Jose) and a number of inexperience ones (say, in
Bangalore). They say it runs something like a truss function in the background and identifies dependencies
that the user might not be aware of (like setup files). They also sell a tool (like LSF) to distribute batch jobs
between different machines.
National Instruments, which sells hardware and software to turn a PC into a basic tester, also sells software
to manage documents. They say they can link requirements documents to test and control applications and
can graphically trace relationships between documents.
License Tools
Flexlm from Macrovision continues its dominance of license daemons, but there are four competitors for
monitoring license usage, and it sounds like any one of them can be the cheapest or most expensive for you
because they are all priced differently.
Flexnetmanager from Macrovision monitors license usage and pricing is done based on the number of
license daemons it will be tracking
LICENSEAnalyzer from OpeniT tracks license usage and pricing is done based on the number of users. You
do not need to officially register users and switch licenses when old employees leave or new employees
start. When you renew the license, the tool prints a report of the number of users per month, and they give
you a little slop to play with. The company also sells graphical tools to monitor usage by division or project, to
monitor your storage and CPU usage, and to take licenses from one user and give them to another. They
have another scary tool that monitors the number of keystrokes, mouse movements and clicks, etc. that
each user does, theoretically to tell when someone has a license out but isn’t using it and also to “improve
the work performance for individuals” and also to “protect employees from computer-related strain and
injury”. Given the history of time and motion studies I suspect this will not be a popular tool.
Runtime Design Automation (www.rtda.com) sells a tool for monitoring license usage. They charge by the
number of machines. The price is about $2500 a year for up to 20 machines. They also have a tool that
allows “what if” analyses of increases or decreases in hardware and licenses. This is always a big deal when
creating next year’s budget so it sounds like something EDA managers would want.
Platform Computing sells a tool for monitoring license usage. I didn’t get any details.
Vendors to other Vendors
Softjin is an Indian company that sells various pieces of EDA tools, including parts of DFM/DFY tools, a
Verilog parser, GDSII and OASIS translators, a GDSII compactor, a schematic generator, and a
programmable synthesis engine for FPGA designs. They will also create tools or flows for customers and do
FPGA design.
Silicon Navigator sells an OpenAccess framework. It is used by EDA companies, internal CAD groups and
sometimes by RTL designers who like their RTL power analysis capability.
Interra Systems sells various language analyzers (System Verilog, Liberty) and synthesis front ends as well
as a generic memory compiler.
Verific sells pieces of tools, such as parsers or readers for Verilog and System Verilog, VHDL, PSL, EDIF,
SDF and Liberty.
Concept Engineering sells viewers and schematic generators for tool vendors.
Other
Silvaco International (which currently owns Simucad) sells a variety of TCAD tools to simulate the
manufacturing process. They also have specialized simulators for light absorption, local thermal effects, thin
films, ferroelectric devices, lasers (first such simulator)
Saratoga Design Systems sells a tool called Flame, which is used for rapid file transfer. They say the speed
for FTP is 40X to 100X faster. They also have the ability to ship only differences between versions.
I missed the Silistix booth this year but saw them last year. They sell tools for a locally synchronous, globally
asynchronous bus structure. The long interconnects are self-timed, which means there are fewer analog
disturbances and also better protection of smart card keys. Comparing themselves to their competitors last
year, they noted that Sonics uses a huge crossbar that is all synchronous, and Arteris uses a clocked
system operating at 4X the system clock, which is power hungry and likely to have timing issues.
Handshake Solutions, a division of Philips, sells IP and tools for clockless logic. There will be a clock at the
interfaces, but internally one might envision an edge that travels endlessly through the circuit. Then an
instruction is started, the edge is sent to a delay circuit that will take slightly longer than the operation, then it
returns to the control logic and goes off to time the next operation. The lack of a clock can reduce power a
great deal. They sell an un-clocked version of the ARM9, called the ARM966HS, which they say uses 2.8X
less power per operation under full load. Operating speed is approximately 50 MHz using a 0.13 micron
process. The lower power means less Electro Magnetic Emissions and also it would be harder to guess what
the chip is doing by monitoring the power supplies (important in secure applications). They say their tool
allows one to use normal standard cells, supports scan testing, and is compatible with normal design tools.
FTL Systems sells a tool that translates VHDL to Verilog and vice versa.
MOSIS combines various small projects onto a single run of wafers to give smaller customer access to large
foundries such as TSMC and IBM, as well as austriamicrosystems and AMIS.
Circuits Multi Projects (CMP) does multi-project wafer runs at austriamicrosystems and ST (down to 65 nm).
They emphasize low prices compared to MOSIS. They also support MEMS.
Doulos sells training in a variety of ASIC and FPGA related areas, including System C, System Verilog,
VHDL, e, PSL, ARM, Xilinx and Altera.
Europractice/IMEC does both design services and shuttle runs from AMI, Austria Microsystems, IHP and
UMC. They support a lot of unusual processes, like high voltage, high speed, and image sensors.
Uniquify is a Santa Clara based company that does design services (they claim RTL to GDSII).
QThink is a San Diego based design services company.
Micro Magic does engineering services, in addition to their tools and IP.
Tata Elxsi does design services (they say spec through GDSII) in Bangalore, India.
TechForce, Inc. is a design service company that can either provide people at your site or send work
“offshore” (Bangalore).
I missed the booth for Time to Market, Inc. which sells layout services. They have offices in the U.S. and India.
Swati Design is a design service company headquartered in California.
In addition to their simulator and IP, Dolphin Integration sells design services.
Parties
Best Party: tough call. Cadence had a very nice “logic designers only” party on Monday, held at the
Automotive museum (neat venue, and in keeping with the official automotive theme), which featured a
drawing for a 2 year lease on a Mustang (or $10,000 cash). The down side was the food; meatloaf, mashed
potatoes and green beans are a little too authentic. Denali had their usual sweaty, shoulder-to-shoulder,
alcohol-fueled, too-loud-to-talk, every-booth-babe-is-invited bash at a downtown nightclub, which was a ton
of fun but not everyone’s cup of tea. The DAC party this year had the best food in years, including unlimited
jumbo shrimp cocktails (get some real cocktail sauce next time!) and mahi-mahi tacos, but for $80 a ticket I
was expecting more entertainment.
Best giveaway: The most popular giveaway was the “pump rocket” from Nascentric. It featured a foam tipped
rocket about 18” long attached to a shoulder-held launcher about the same length. The most popular
drawing was for the X-box 360 that Cadence gave away every hour on the hour at the “Common Platform”
(IBM/Chartered/Samsung) booth. Your best chance for a good gift though was at Cliosoft. They had a poker
game every hour with six seats (usually 4 or 5 players) and the winner got an iPod Shuffle. If everyone had
the same skills you have a 20% change of winning; if you can play poker maybe more like a 50% chance. I
now own a Shuffle. Dang, those things are small.
Worst giveaway: OneSpin Solutions once again gave a way a puzzle. Last year I picked up one and tried
solving it at the booth (which would enter me in a drawing). The salesman started laughing and said it wasn’t
the kind of puzzle you could solve in just 5 or 10 minutes (I think it had 9 factorial times 4 to the eighth ways
of arranging the nearly identical pieces). I woke up early one morning last year and spend another half hour
on it – no luck. This year I passed; who comes to DAC to spend hours on a puzzle?