Trip Report - 2005 Design Automation Conference (DAC)
John Weiland, Intrinsix Corp.
Please note that the opinions expressed here represent those of the author, not of Intrinsix Corp. or
any other organization.
Given the huge number of companies that I am reporting on, there will no doubt be some errors in this
report - please accept my apologies for this. Also note that the companies listed under each category
are in basically random order; please do not draw any conclusions based on who is listed first.
General
In general this seemed like last the DAC and healthier than the previous few. The aisles got a bit
crowded at points but still lacked the attendance of the bigger DACs in the past. We’ll know the good
times are back (and maybe about to end) when Synopsys and Cadence are throwing lavish parties
again. No reports of homeless engineer/goat farmers like last year in San Diego’s Gaslight District.
Industry Overview
Gartner Dataquest/EDAC
Dataquest did their usual industry roundup on Sunday might, which is always worth attending. Video
games and cell phones are currently driving ASIC quantities. Last year they called for 2005 to be a
great year and 2006 to be a downturn. As it turns out 2005 was an OK year and they are now calling
for the downturn in 2009. They predict that by 2008 one third of all ASICs will be “platform based”, by
which they mean at least half of the ASIC will be blocks that are being reused. TI has done remarkably
well in the last year, with 36% growth fueled primarily by their DSP expertise.
The IP race is still headed by ARM with Synopsys (including Designware) holding the number 4 slot
and Mentor is ninth. EDA companies are not as strong in this area as many believe. Analog IP is a
small but rapidly growing segment however it is hampered by the fact that analog IP often needs
optimization for the specific system. Gartner also thought the cost of designing for reuse is higher with
analog than with digital IP. Gary Smith thought the real price pressure for EDA was what it would cost
to internally develop a comparable tool. By that standard, he thought EDA was a bargain, due to
recent price wars between the major companies. He feels that future EDA growth will be in the
Electronic System Level (ESL) tools. When RTL synthesis took over from schematic entry, there was a
4X improvement in productivity, and he wondered if ESL might do something similar. Gary also said
many customers are getting out of layout and want to just hand off RTL. EDAC now has a roadmap for
which of the myriad of PC operating systems will be supported during what time period.
Keynote Address
Tuesday opened with another strong keynote address delivered by Bernie Meyerson of IBM on the
paradox of interpreting Moore’s Law. Meyerson said that Moore’s law applies only to density, but
people have universalized its interpretation to mean that everything (size, speed, power, etc.) scales
every year.
He said that classical scaling involves scaling everything, including oxide thicknesses, dopant levels,
and source/drain depth, and it has already broken down. For example, oxide thicknesses stopped
scaling when they hit about 5 atoms thick. They should now be about two and a half atoms thick but it’s
hard to get the half atom. Similarly voltage levels have not scaled. Scaling has basically run out of gas
because we’re dealing with geometries that are close to the size of atoms. He compared it to a bathtub
full of wet sand. If you press your hand into it, you will leave an imprint that is pretty detailed and will
probably include some of the lines on your hand. If you fill the tub full of marbles and press your hand
in, it will leave an indentation but not very detailed; it won’t even look like a hand. If you fill it full of
bowling balls, there is no way to even leave a handprint.
He said that fundamentally scaling is about power density. If changes continue going this way,
Meyerson quipped that in the future “you will need helicopter mounted to every microprocessor”. He
predicted that further advances will rely on many innovations, some large and some small, rather than
continued scaling. For example, most 90 nm processes now use strained silicon, which improves P
mobility about 30% and N mobility about 20%. Experimentation with low K dielectric will continue but he
emphasized that the lower the K, the weaker the material, so there is a limit to this technique for
increasing speed.
The Thursday keynote by Ron Rohrer was on “Innovation in the EDA Business”. He stressed that no
product is based on a single new, big idea; all products require many minor innovations to become
salable. He suggested ideas are worthless; implementation is everything. He stressed that engineers
should look for what is good in a new idea (rather than pointing out the inevitable flaws) and think of it
as a part of a new product. He also emphasized the need to negotiate realistic expectations with EDA
customers. For example, everyone wants speed, accuracy and capacity, but one must choose how to
trade those off. He also noted that the more quality problems a product has, the more R&D resources
become involved in servicing customers, which will kill future innovation. For the overall process of
going from an idea to a product, he felt it took roughly 6 years and initially should be staffed by 3-5
people (he felt 10 was far too many). He emphasized the need for patience while a new product is in
beta and also did a very interesting calculation that indicated the industry can only sustain a total of
about 150 products (far fewer than what one sees on the DAC floor).
X Initiative
Work progresses on using 45-degree angles in everyday chips. Thus far the alliance doing the
research has concluded that the bottom 3 metal layers should be 90 degree, topped by metal 4 and 5
that should be 45 degree. If additional layers prove to be required the next two metal layers should be
at 90 degrees and two more at 45 degrees. They claim up to 20% total wire length reduction and up to
30% reduction in the number of vias. ARM did a design that was 16% faster and 10% smaller with 45
degree routing.
ATI re-implemented a PCI Express graphics chip that they had already done in 0.11 micron technology
using ordinary Manhattan technology. This re-implemented chip utilizes the same IP, packages, etc.
with 6 metal layers that reduced fab costs. Rather than trying to make it smaller, they dropped from 7
metal layers to 6, which would have been impossible with Manhattan. TSMC has rules for 45 degrees
at 90 nm and is developing rules at 65 nm.
Cadence emphasized that X technology affects more than just routing. Cadence has been telling Wall
Street that their participation in this initiative will give them a strategic advantage. Talking about the
need for a whole flow rather than just some custom setup files for a router will give them an edge, but
may also frighten customers who already think this is exotic and may not want to be stuck with a single
vendor’s tools. They talked about how X affects optimum power stripes and also pin placement. On a
Manhattan chip, the area of all possible pin locations within some distance of a given point is a
diamond shape. In X technology this becomes an octagon – increasing usable area without increasing
routing length. Cadence said it took some work to extend Fire and Ice to X technology because there
were a number of new geometries to worry about. LEF/DEF now supports X as well.
Standards
System Verilog seemed to be more universally popular this year with the Accellera team as one of its
most vocal advocates. At the 2003 DAC, Cadence had just jumped on the System C bandwagon that
Synopsys had jumped on earlier, only to have Synopsys jump off and onto the System Verilog
bandwagon. Cadence folks badmouthed System Verilog at every opportunity, while Synopsys folks
said System C was for system design and System Verilog (which was a misnomer according to them)
was for detailed implementation. Anyway, two years later Cadence has enlarged their reach to
embrace System C and System Verilog but also “e” language as well. Anecdotally it sounds like there
is still very little actual design being done with SV; designers might be waiting until an entire flow is
ready and proven and they have options on major tools.
Si2 (Silicon Integration Initiative) had a booth again and was pushing the OpenAccess standard, which
in the past has often meant the “companies who want Cadence to buy them” standard. Silicon
Navigator sells a framework built on OpenAccess for tool vendors and internal CAD groups, so anyone
can have an OpenAccess EDA system.
Conference Talks
I attended a talk on soft errors which concluded that most soft errors are actually benign. Many factors
were considered in reaching this conclusion. First off, many glitches aren’t observable (in the
testability sense) or aren’t caught by the downstream flop because of timing relative to the clock.
Beyond that, they can occur during dead instructions, occur in currently unused circuitry, cause
packets to be retransmitted, etc. The biggest fear is silent data corruption. Lowering supply voltages
increases soft error rate but making devices smaller decreases the rate, so the soft error rate per gate
stays roughly constant as technologies scale. The hypothesis is that error rates are roughly doubling
with each new technology because there are more gates in each new technology. Current proposed
solutions to soft errors are circuit hardening or redundancy. In terms of hardening, SOI has 5X to 8X
fewer soft errors. For redundancy, one author recommended using a tri-state followed by a bus
keeper to protect important flops, asserting that this would save huge amounts of areas versus
duplicating circuitry and comparing or voting.
There was a Cadence/IBM panel discussion centered on whether ASICs were the answer at 65 nm.
Their claim was that as feature sizes shrink, the number of engineers needed to do front end work for
a given size chip stays roughly constant (use of more and bigger IP?) but the number of back end
designers explodes with increasing potential for problems with SI and the like. Anyway, they thought
that ASICs might be the answer for most customers and people might get away from a COT flow. In
2002 there was a DAC panel about ASIC handoff that theorized that no one will be tossing a netlist
over the wall any more, but theorized they would be handing off either placed gates or RTL. One
panelist projected that the power users would use placed gates and the rest would use RTL. Another
theorized that RTL handoffs might not work because no one really thinks about false and multi-cycle
paths until they get stuck doing synthesis; having synthesis done in a completely different organization
from coding would make this a major problem. Anyway, if you believe that the back end just keeps
getting worse, then placed gate handoff might be difficult and RTL handoff might be the way to go.
Certainly there are now tools to help identify false and multi-cycle paths.
High Level Design/ESL/C Based Design
Another presentation entitled “ESL, tales from the trenches” proved very thought provoking. One
speaker said that system engineers use a disconnected mishmash of tools. They typically use MS
Word for writing a spec, then Matlab for simulating an algorithm, then MS excel or System C for
architectural definition, then an HDL and ISS to do detailed simulation of hardware and software. In
particular, the speaker felt tools were missing to do architectural tradeoffs. He felt some sort of
executable spec was needed, possibly UML. They also commented how most training is in languages,
not methodologies. For most methodologies, 20% of the language constructs are used 80% of the
time. There is a big difference between showing someone a diagram of all the parts of a car and
teaching them how to drive.
Some ESL-related tools in random order:
Synfora sells a behavioral synthesis tool that accepts ANSI C and a constraint file and produces
synthesizable Verilog RTL, synthesis scripts, and testbenches.
Forte Design Systems sells a behavioral synthesis tool that goes from System C to Verilog RTL. They
emphasized that it is production proven.
Mentor’s “Catapult” goes from C++ (with no timing in the code) to RTL. They emphasize that they take
standard ANSI C++ as input but support System C data types. It builds RAM interfaces automatically.
You also need to specify clock rate and other constraints as an input. Outputs are cycle accurate
VHDL, Verilog and System C (for simulation) and VHDL and Verilog RTL. Unlike Celoxica’s tool, theirs
inserts registers automatically based on constraints. Their tool is probably not as good at what-if
analysis or HW/SW tradeoffs. They say it’s aimed mainly at dataflow applications with minimal control
issues.
VaST Systems sells models for common processors, allowing users to do virtual prototyping to debug
software. These models are cycle accurate at an architectural level and help with bus structure, cache
sizes, etc. They are intended for hardware/software codesign: software engineers can write their code
while hardware engineers create more detailed models.
Carbon Design sells C based verification systems (the symbol for Carbon is “C” – get it?). They
emphasized that C based simulation systems are much faster than RTL. They also highlighted the
cost advantages that once you get the system running you get as many copies as you need for free,
unlike hardware based systems. Their system accepts RTL in and can connect to models from
CoWare, VaST and ARM.
Tenison EDA sells tools for converting Verilog models into C and C++ models for verification and
software/firmware development. They have various tools for linking models with firmware, testing C
models versus RTL, and exporting stand-alone models. VHDL tools are in development.
Bellum Software sells a graphical tool that allows the user to design and simulate at the transaction
level. The say this allows rapid debugging of protocols and exploration of new architectures.
CoFluent Design is a French company that sells a high level graphical tool. The input is a graphical
model plus some C code for functionality. The output is a C++ executable model, similar to a Matlab
level model, used for timed behavioral modeling. They say their system can mix control and data flow
on the same diagram. Their goal is helping system architects quickly do tradeoffs.
Bluespec sells a tool that takes extensions to System Verilog that basically describes constraints on
your design, and outputs Verilog RTL and cycle accurate C models. They claim to average roughly a
50% time savings (in one case as much as 80%) in getting to a verified netlist, but say customer
evaluations have shown only 2-3 days of training is necessary to become productive.
CoWare sells a suite of System C tools including what they claim is the fastest System C simulator
presently available. These tools have the ability to mix transaction level System C models and VHDL or
Verilog RTL and support for ARM and MIPS. CoWare claims they can simulate an SOC at 10-20 MIPS
(last year it was 300-500 KIPS) enabling you to try out your system software. They also have tools
they got from LISATek, which use their Language for Instruction Set Architectures (LISA) for rapid
generation of RTL code as well as compilers, assemblers, etc. They also recently bought the SPW
signal processing tools from Cadence.
YXI sells a tool that goes from ANSI C to VHDL or Verilog RTL. They also have worked with Renesas
and now can use the HyC language, which has more timing information than untimed C.
NEC has been using C based tools for 10 years and is now offering them to customers. They have
translators from C to VHDL or Verilog and vice versa and also an equivalence checker than can
compare the two. It can also generate bus interfaces like AMBA and AHB and includes a formal
property checker as well as a floorplanner. These tools can produce a cycle accurate C model for ISS.
NEC asserts that most of their bugs are now found in C simulation, not RTL.
Simantix Systems has a simulation and development tool for their language called Visual MetaSL,
which is based on the IEEE 1990 Scheme standard. This language is intended to be an executable
spec at a higher level than C language due to its many high level functions. It is intended to be a
single source for both the design and the testbenches. The MetaSL language and tool allows for
multiple clocks and multi-threading. Everything is compiled to C. They have links to Verilog and can co-
simulate Scheme, C, C++ and Verilog. They also have project and library management tools.
Giga Scale IC makes a tool called InCyte that estimates die size, power, leakage, yield and speed.
They claim results are within 10% of silicon. The tool comes with a large library of IP cores.
Applied Wave Research sells a tool to overall design of communications systems. Unlike C/C++ based
tools, this one is aimed mostly at analog and RF communications and can simulate things like bit error
rates.
Accelchip sells a synthesis tool that takes a MATLAB model, converts it to fixed-point arithmetic and
produces synthesizable VHDL or Verilog. They can now export to Simulink and Xilinx. They have
added the ability to insert pipeline stages and unroll “for” loops.
Synplicity sells a tool called Synplify DSP that accepts a MATLAB/Simulink description of your
algorithm plus some user inputs from a GUI and produces synthesizable RTL for FPGAs and a
testbench. This tool also can be targeted to an ASIC but you have to massage the result for RAM
instantiations.
Poseidon Design Systems sells two tools. The first is a C based system that analyzes the software on
the system architecture, performing transaction level co-simulation to identify bottlenecks. The second
creates an FPGA accelerator for slow instructions and creates the interface for the processor to the
FPGA.
Synopsys has an IP reuse tool called Core Assembler. It knows signal types and can automatically
connect some ports when you drop down several pieces of IP. It adds verification models for some IP
and can create a testbench shell. A related tool called Core Builder adds new cores to the library.
Synopsys also sells System Studio, a tool to help with algorithm development, architectural exploration
and software integration. They emphasized that the most costly mistakes are architectural mistakes.
The tool uses dataflow models for some components and System C for others. Synopsys plans to
distribute their own models and third party vendors will distribute other models. The debug GUI
supports System C, System Verilog, Verilog and VHDL at both the RTL and transaction level.
Transaction level System Verilog is in beta, and functional coverage for that language is coming.
Jeda Technology sells System C assertions that are similar to System Verilog assertions. They are
native to System C and provide assertion coverage. Currently they do not tie into any scoreboard.
Atrenta sells a tool called “1 team implement” comprised of three pieces. The first section is for system
architects and partitions RTL, coming up with timing, area budgets, etc. The second gives RTL coders
access to physical results without having to know how to do place and route. The last element is a
mixed hard macro and standard cell floorplanner. The tool is built on OpenAccess and is fully native.
The output is a floorplan and placed gates. The tool can do synthesis internally but Atrenta
recommends use of a real synthesis tool for final results. BTW, Atrenta was just a linter company last
year. They now employ 230 people and apparently Synopsys is not pleased with their invasion of new
turf.
Summit has a new tool that uses pre-built System C libraries to optimize for power and performance.
The power numbers come from IP vendor spec sheets, not some pre-characterization process like
some tools. The tool allows for tradeoffs and what-if analysis and can simulate the design for software
development.
Prosilog sells a GUI environment to help with easy IP integration. It generates synthesizable RTL and
well as make files for synthesis and supports the connections between blocks.
Design Entry
Stellar Design sells graphical tools to help the user create high-level code, stitch them together, and
move signals up and down in the hierarchy. It shows the overall hierarchy and file dependencies, and
hence can aid in understanding legacy code as well as do data mining for other tools. It also supports
assertions and constraints and can help enforce specific design flows including some linting type
checks as well as fix some errors (like synchronizing between clock domains). Their claim is that the
checks are so fast you can run them after each change, rather than waiting until the end of the day.
The tool is currently VHDL only with Verilog in beta, and runs on Linux or XP.
Semantic Designs sells a variety of tools for coding. They do things like create a standard appearance
for code, detect and eliminate dead code, and detect redundant code blocks and create single
tasks/functions to replace them.
Summit continues to sell their tools that go from pictures to VHDL, Verilog and System C, and vice
versa, but have gotten more into other areas of System C.
Intellectual Property
Beach Solutions has a system for capturing design information about a system or about IP and
checking it for consistency and conformity to various rules, then producing reports in user-
customizable formats. They also bought software from the VCX for cataloging and presenting IP to
customers. They say that having all data start from a single source and managed through single–
source reports is key to preventing expensive mistakes. One customer estimated a savings of $50M
over a 5-year period using this product – quite a claim.
Denali sells their Databahn IP for interfaces to serial ATA and SDR, DDR and now DDR2 running up to
400 MHz. Their Dataplex IP handles off chip storage using interfaces like SATA, Flash and DDR. For
verification IP, Denali sells a variety of products to verify interfaces to memory and standard interfaces
like serial ATA, PCI Express, and Advanced Switching Interconnect. Their PureSpec tool now has API
to hook to Verisity and Vera.
DAFCA is a new startup that sells wrappers for testing IP. They say their wrappers enable real-time
access of internal signals, at-speed observability and can support debug as well. The wrappers can
use any of several interface formats including P1500. The company had no booth, only a demo suite,
but they were very popular.
Design and Reuse and the Virtual Component Exchange seem to be getting more similar as time
progresses. While the Scottish government was subsidizing the VCX it was addressing overall industry
problems with IP, but now that they are on their own they seem to be slowly turning into a simple
storefront like D&R.
CAST sells a wide variety of cores, including processors, various standard interfaces, and multimedia
and encryption blocks. Most cores are available as synthesizable VHDL or optimized for Altera or Xilinx.
Tensilica is promoting a processor designed so that it is easy for the user to add new instructions.
They have a new capability to analyze the users program to identify slow spots and show how to
extend the processor.
Synfora sells a customizable VLIW processor but they say they can do the rest of the system as well
using their C language behavioral synthesis. Their tool creates a number of versions of the processor
and allows the user to make speed/area/power tradeoffs. They have pre-characterized TSMC 0.13
library and say they can quickly bring up other libraries using scripts. Unlike some competitors, it is
now possible for the user to assemble custom instructions. Synfora accomplishes this using a C and
Verilog description from the user. The tool is sold on ease of use rather than configurability.
Silicon Image sells a variety of cores for HDMI, DVI, SATA and Fiber Channel.
Cambridge Consultants sells 16 and 32 bit XAP processors and also a datapath signal-processing
engine.
Accelchip sells parameterized DSP cores such as filters, FFT blocks, and forward error correction and
math functions.
Flexeos sells embedded FPGA cores that one can put on an ASIC or SOC. They deliver instances to
order however they do not sell their generator. They deliver the GDSII, test vectors, and software to
program it. The cell is SRAM based so it is very transportable. They are now doing test chips with
Taiwanese fabs.
QualCore Logic sells a variety of analog and digital IP, including DACs, ADCs, DLLs, LVDS pads, an
Ethernet MAC, and controllers for SATA, PCI and USB.
LTRIM is a Canadian analog IP provider. They provide ADCs and also high efficiency DC to DC
converters. They provide support for TSMC, IBM (8rf), SMIC and Polar Fab. They claim they are
particularly good at tweaking IP for particular customer’s needs providing a somewhat unique service
to clients (Note: many providers don’t like doing this). Their name comes from the fact that they use a
laser to make fine-tuning in the circuit rather than fuses.
Nordic Semiconductor sells ADC and DAC IP, typically 10-12 bits and 10-200 M samples. Their
designs are mostly for TSMC and UMC with some support for Chartered and IBM. They will tweak IP for
customers if the result appears to be resalable.
True Circuits, Inc. sells analog IP, mostly PLLs and DLLs. They also have done DACs, SERDES, etc.
but say that’s not their main business. Their circuits are designed for TSMC, UMC, Charter and many
IDM fabs for technologies ranging from 0.25 to 90 nm. They are doing test chips at 65 nm. They
represent their IP as very programmable and they can customize them if the results might be resalable.
Dolphin Integration sells a variety of mixed signal IP and emphasized low power design.
Synopsys sells a variety of Designware cores and says that if you include their free Designware, they
are the largest provider of IP. Their not-so-free cores include USB and PCI-whatever and they have a
variety of verification IP as well.
Knowlent Corp. sells verification IP for various standard analog interfaces like PCI and serial ATA.
They market their products based on their participation on many standards committees, enabling them
to be at the leading edge in product testing.
Cologne Chip sells analog IP that is implemented entirely with digital circuits. The offerings include
Phase Locked Loops and CODECs. The 100 digital implementation means you can fabricate the IP
anywhere, even in an FPGA.
Gaisler Research sells a 32 bit user-customizable SPARC V8 core that competes against ARM and
ARC. Anyone can download the VHDL; they sell commercial licenses as well as peripherals, OS,
software simulator, and hardware debug monitor. They say their core is about 1/10 the cost of an ARM.
Ignios sells IP to make programming of multicore processors easier. They say it will distribute tasks on
either homogeneous or heterogeneous designs. Their “System Weaver” tool swill support up to 32
processors. They had one demo with 16 ARM processors and another with two Power PC processors.
Kilopass Technology sells one-time programmable nonvolatile memories using standard CMOS
processes, including TSMC 0.18 and UMC 0.13.
Sarnoff Labs sells IP for ESD protection, and are now targeting fables markets. Their IP will work for
TSMC 0.18 and 0.13 technologies.
The Open Core Protocol partnership had a booth to promote their standard for plug-and-play IP.
S2C (System 2 Chip) sells an interesting mix of technology. They have a method for encrypting IP that
can only be used by their FPGA prototyping system. A user can try out IP in an actual system design
and simulate it on their system, which supports up to 3 million ASIC gates. They do not support any
other proto boards.
Semantic Designs sells VHDL and Verilog obfuscators (a tool that renames nets and instances to
make it harder to understand what’s going on). This is used to help protect IP.
YXI has what I thought (several years ago) was a really neat tool. You would describe IP in their format
and when you wanted to use it the tool would create the interface to the environment of the IP, even
modifying state machines if necessary. Unfortunately you had to model the IP for their system, which
didn’t seem to happen for any major IP. The main use was for internal IP at Japanese companies. This
year they de-emphasized this tool at the booth and sent Japanese speaking A.E.s to man the booth.
Prosilog sells several tools to help package and use IP. They have a tool that creates standard Open
Core Protocol interfaces for your IP, and another that will create a SPIRIT 1.0 standard description of it.
Design Reuse
Synopsys has an IP reuse tool called Core Assembler (and another one called Core Builder to add
new cores to the library). It knows signal types and can automatically connect some ports when you
drop down several pieces of IP. It adds verification models for some IP and can create a testbench
shell.
Stellar Tools sells a graphical tool that helps a designer see hierarchy, dependencies, etc. in legacy
code. The tool is currently VHDL only with Verilog in beta, and runs on Linux or XP.
YXI has what I thought (several years ago) was a really neat tool. You would describe IP in their format
and when you wanted to use it the tool would create the interface to the environment of the IP, even
modifying state machines if necessary. Unfortunately you had to model the IP for their system, which
didn’t seem to happen for any major IP. The main use was for internal IP at Japanese companies. This
year they de-emphasized this tool at the booth and sent Japanese speaking A.E.s to man the booth.
Logic Synthesis
Incentia Design Systems sells synthesis tools that are compatible with Design Compiler and Physical
Compiler. They support low power design and have Designware. Most customers are in Asia, and
include NEC, Toshiba and Cisco.
SynApps sells tools for synthesis, static timing analysis, placement and clock tree insertion. The tools
have aliases that allow the use of most Primetime commands and many Design Compiler commands.
They say their STA tool is 20% faster than Primetime and currently the synthesis and STA tool go for
only $5K/month.
FTL Systems has a logic synthesis tool (VHDL or Verilog) in beta with two clients and says results are
available. The tool is expected to ship in 4Q05. They say they have limited Designware equivalents.
Hardware/Software Coverification
ACE (Associated Compiler Experts) sells software for compiler development. They say this rapid
compiler development environment allows for fast exploration of alternative architectures. They have a
new release of their tools.
Obsidian Software sells a tool that generates random instructions at RTL level based on user-defined
templates. They support X86, ARM, MIPS, X86, DSPs, etc. or any custom processor description.
Simulators
Mentor now sells Questa Sim, which is Modelsim with some extra verification stuff. The (overly?)
honest A.E. at the booth said that people assume Modelsim is just a simulator so they aren’t willing to
pay any more for it no matter what is added. Questa takes SystemVerilog and PSL assertions. They
claim it is the first simulator to do assertions and functional coverage natively.
Synopsys brought out VCS-MX a year or two ago to add VHDL capability to their highly successful
Verilog simulator. It did not take the world by storm. The A.E. at the booth claimed the VHDL capability
in VCS-MX had outstanding capacity but wasn’t easy to use, and also claimed that Mentor’s VHDL had
extra things that did not comply with the IEEE standard but Synopsys eventually added them to meet
customer’s expectations. Anyway, they claim they are faster than Mentor. They are adding System
Verilog assertions to VHDL. There are no plans to support PSL at present. Their new DVE GU
supports VHDL, Verilog, System C and System Verilog. They have just added free code coverage for
VHDL, which includes condition and path coverage.
FTL Systems sells a simulator for Verilog, VHDL, analog and microwave/RF. They claim it runs on up
to 128 processors.
Axiom (formerly @HDL) expanded from the formal verification realm into simulators. They have a
System Verilog simulator that they claim is specifically designed for a multiprocessor environment.
They say that with 4 CPUs it is about 3X faster and with 8 CPUs it’s about 5X faster. These assertions
are in line with what I’d expect since at some point the inter-processor communication overhead
swamps out your CPU power. They have also introduced a debug environment that they claim is
similar to NOVAS Verdi.
Aldec has an inexpensive simulator that takes VHDL, Verilog, C/C++, System C, System Verilog, PSL,
and OVA. They also sell a hardware accelerator that contains 12M FPGA gates per board and can
take an ARM daughter board for software verification and acceleration.
Silvaco sells the old Silos simulator and is upgrading it to be Verilog 2001 compliant. After years of
being a major player in the analog realm they are ready to enter the digital fray. This will be a single
kernel analog/Verilog simulator.
Fintronics sells an inexpensive simulator that can mix C, C++ and Verilog. System C is coming soon.
Currently there is no VHDL support.
EverCAD sells a simulator that combines SPICE (they claim 2X-3X faster than SPICE), a table-driven
SPICE-like simulator (they claim 2X-3X faster than HSIM) and a Verilog simulator, plus it ties into major
VHDL/Verilog simulator and Spectre.
Avery Design Systems sells a tool to partition the simulation task among different processors. This
claim is noteworthy since this is not one of the easier tasks to split up.
Hardware Accelerators, Emulators and Prototyping Systems
Be very careful when any of the accelerator, emulator or prototyping people talk about gate counts.
Any FPGA based system tends to get low utilization and the difference between the number of ASIC
gates they are modeling and the number of FPGA gates they are actually using can be a factor of 5 to
10 or even more. I try to keep it straight about which they are talking about but sometimes I get it
wrong.
Gidel sells new boards using Cyclone II and Stratix II parts. They can model up to 9 M ASIC gates per
board. Chip to chip clock rates are theoretically up to 500 MHZ but more likely around 250 MHz, and
board to board interconnect can be 500 MHz with DDR.
Dini has a new board that uses Vertex 4 devices. Each board can emulate 3-7 million ASIC gates.
They feature 500 MHZ chip-to-chip communication and up to 10 GHZ board-to-board. They
emphasized that there is no overhead on the Virtex parts; they have a separate PCI controller. They
also have on-board power supplies. With 1800 IO they hope for fewer portioning problems.
Hardi Electronics sells prototyping FPGA boards with a unique interconnect structure between them.
One board can have up to 3 M gates and they claim one can stack an unlimited number of boards.
Chip-to-chip and board-to-board speeds are up to 200 MHz. They can have up to 20 daughter cards
so many options are possible.
ChipIt sells prototyping boards with up to 1.6 million ASIC gates per board and up to 6 boards per
system. Boards run up to 200 MHz on board and around 100 MHz between boards.
Aldec sells a hardware accelerator that contains 12M FPGA gates (1M-2M ASIC gates) per board and
can take an ARM daughter board for software verification and acceleration.
S2C (System 2 Chip) sells an interesting mix of technology. They have a method for encrypting IP that
can only be used by their FPGA prototyping system. A user can try out IP in an actual system design
and simulate it on their system, which supports up to 3 million ASIC gates. They do not support any
other proto boards.
Cadence bought Verisity, which means they now sell the former Axis Design boxes as well as the
boxes from Quickturn, which they acquired 7 or 8 years ago. At a lunch I attended they announced
plans to continue selling both products. They said the event driven Xtreme boxes are better for block
level simulation and are also easier to get up and running if you already have a software simulation
functioning. This basically assumes that a customer might buy one box or set of boxes for block level
simulation and another for chip and system level simulation. Given the price of these boxes that’s quite
an assumption for most customers.
Tharas sells hardware accelerators, possibly the only true hardware accelerators left. Their new
system has up to 256 M ASIC gates and runs at 200 KHz featuring a new transaction level interface.
Dynalith sells a small, inexpensive FPGA prototyping board. This board has 10M-20M FPGA gates (2-
3 million ASIC gates) using Virtex 4 parts and it goes in the back of a PC. It runs at up to 66 MHz.
EVE sells a product that they claim is has nearly the speed of an FPGA proto board but is as easy to
debug as an emulator. Their system supports up to 50 M ASIC gates. It has always been transactor
based but was sometimes slowed while it waited for a Verilog testbench to catch up. They can now use
System Verilog so they say they get faster transactors plus SV assertions. Their compiler now handles
multiple clocks without user intervention. They were proud of a small board with four Virtex 4-200 parts
running at 60 MHz.
FTL Systems says they are developing a hardware accelerator for analog simulation. They claim the
4U form factor box will have teraop processing power and will also be available for use as a
supercomputer.
Synplicity sells a tool called Certify to split up an ASIC design into multiple FPGAs for prototyping.
BYO Solutions is still in stealth mode – more to be revealed later.
Linters
As with code coverage tools, linters are being given away free with some simulators now and I was
interested to see if that affected sales of other linters, but I couldn’t get a read on this. Note that many
linters already have things that differentiate them.
The Atrenta folks would have a cow if I called their tool a linter; they say they sell “predictive
analyzers”. They do a synthesis to generic gates which they say allows them to check for some things
that ordinary linter cannot.
The Synopsys Leda linter also seems to do synthesis to generic gates and is highly programmable
even without the separate and expensive tool to customize it.
Cadence has been giving away their Hal linter for years now with the purchase of NC-Sim. They are
expanding capabilities and it is programmable.
VeriEZ sells tools for openVera and System Verilog; the latter offerings are new this year. They sell a
linter for both languages, a rule builder for that linter, and a “knowledge extractor” that can tell you
about hierarchy, concurrency, etc. in your Vera or System Verilog code. They also have a tool to
translate Vera to System Verilog.
Code Coverage
The code coverage tools being included free with simulators nowadays are in some cases pretty good.
TransEDA has an outstanding tool but has to constantly improve it to stay ahead of the free
competitors. They are now offering assertion coverage. SVA is available now and PSL is coming in
4Q05. They say their assertion coverage is more in depth than competitors. For example, they can
look at condition coverage or seek where different variables in the assertion are being assigned.
Synopsys says they have just added free code coverage for VHDL with VCS-MX, which includes
condition and path coverage.
Debug Environments
Novas sells Debussy and Verdi, two debug environments. Verdi is a superset of Debussy with RTL
debug features. They support VHDL, Verilog, e, Vera, System Verilog and PSL. System C support is
coming in November. They can trace backwards to drivers or forward to loads, can find the causes of
transitions, and can read the output of Primetime or DC directly and show critical paths. They have a
special clock tree schematic mod where all loads on a single driver are lumped, and they have a clock
domain checker. They have add-on modules to monitor transactions on standard buses (they sell
OEM products from Denali and SpiraTech) and the System-C stuff will be an extra module.
Veritools sells the less expensive Undertow tool in competition with Debussy and Verdi. It allows “X”
tracing through logic levels and clock times. They are also adding System Verilog Assertions, which will
be compiled within their tool.
Axiom (formerly @HDL) has introduced a debug environment that they claim is similar to the Novas
Verdi tool. This environment integrates with their new multiprocessor System Verilog simulator.
Summit sells a System C debugger and design environment that they compare to Verdi except it’s for
System C.
Functional Verification
Formal Tools
Calypto makes what they say is the first sequential equivalence checker. Normal equivalence checkers
compare the clouds of logic between registers in a design. If you add an extra register or move one it
makes the clouds of logic unequal and it either takes more time (if it’s possible at all) or requires some
hints about what’s been changed. The key feature of this new tool is its represented ability to compare
two versions of a design with completely different timing. For example, they claim they can compare
System C (untimed) to RTL. They are not as fast for gate level comparisons and have smaller
capacity, so they recommend using existing tools for that purpose.
Jasper Design Automation sells a formal tool that is guaranteed to reach a conclusion – quite a claim
given how uncertain it is that you will ever have enough CPU cycles to reach a conclusion. The trick is
that the user is supposed to interact with the tool and snip away situations in the state space that don’t
matter. Assertions are at a high level, rather than low-level situations like a FIFO not filling up. They
acquired Safelogic a Swedish company that had a PSL formal tool. As a result, Jasper now takes PSL,
and System Verilog is coming in the fall.
Real Intent was probably the first company to automatically generate assertions based on RTL code
and try to prove or disprove them. They have added the capability for users to specify assertions as
well. They also check clock domain crossing automatically.
Atrenta sells a new tool called “1 team verify”. It automatically generates implicit assertions (like FSM
deadlock or overflow/underflow) and they recognize handshakes in FIFOs so they apply assertions
there. They are also working on full chip analysis (which they say is a challenging problem) in the area
of clock domain crossings.
Averant sells a property verifier that accepts both PSL and SVA, as well having their own language.
They say most users prefer the Averant language, even though simulators do not support it. Their tool
does automatic design checks for deadlock, clock domain crossing, etc. and they say it is really good
on large designs. They have another tool that verifies whether or not a design meets a certain bus
protocol (like AHB, AXI or APB). It does this without simulation. They say it takes roughly an hour to run
on a typical design once it is set up with a GUI.
@HDL has changed their name to Axiom, which probably makes it much easier on the folks making
phone books. They have a model checker that can use System Verilog assertions or PSL, and also a
clock domain formal tool that can find and fix problems. They have recently moved into the
simulator/debug environment realm as well.
Mentor’s 0-In folks say they have new capabilities in their clock-checking tool, specifically checking for
clock domain re-convergence. They say they can now check a device with hundreds of clocks.
Testbench Generation & Semi-Formal Tools
Cadence’s purchase of Verisity generated a great deal of interest in how this would fit into their plans.
In 2003, they had just jumped on the System C bandwagon (joining Synopsys) only to have Synopsys
jump off and onto the System Verilog bandwagon. At that point, Cadence played up System C and
badmouthed System Verilog, while Synopsys said System C was for system design while the misnamed
System Verilog was more for detailed implementation; hence Synopsys claimed they did not really
compete. Cadence has since enlarged their grasp to embrace both of those languages and “e”
language as well.
I attended a lunch where they outlined their future usage for all three languages. They drew a chart
with four quadrants – system design, system verification, chip and block design, and chip and block
verification. They showed System C in the system design area with a very slight involvement in system
verification. They showed System Verilog in the chip and block level design area with some
involvement in chip and block verification. “E” language was involved in all levels of verification,
including “project level”, whatever that meant. Regardless, they clearly believe that “e”, system C and
System Verilog will coexist. Amazingly, they predicted that System Verilog might slowly infringe more
and more on what is now done with “e”. They said “e” would be around for a long time because so
much verification IP has been written in it, but they seemed to be suggesting that SV might eventually
supplant it. On the other hand, they talked at their booth about plans to create a single kernel
Specman/NS-Sim tools with a single GUI; that should be easy to sell.
ARM also spoke and said they hope to supply SVA functional coverage to their customers in the near
future. Interestingly, Cadence also said they plan to continue selling both the Axis boxes they acquired
with Verisity and the Quickturn boxes they acquired years ago. See additional review, page 13.
SpiraTech sells transactors for various standard buses like PCI, etc. They also sell hooks for it to be
utilized with NOVAS Verdi as well as a generator for creating new transactors. They use a language
called “CY” which they claim is 5X-10X faster than writing the transactor in C++.
Avery Design Systems sells verification IP for PCI Express and serial ATA
VeriEZ sells tools for openVera and (new this year) System Verilog. They sell a linter for both
languages, a rule builder for that linter, and a “knowledge extractor” that can tell you about hierarchy,
concurrency, etc. in your Vera or System Verilog code. They also have a tool to translate Vera to
System Verilog.
Jeda Technology sells System C assertions that are similar to System Verilog assertions. They are
native to System C and provide assertion coverage. Currently they do not tie into any scoreboard.
TeamEDA sells a tool that is supposed to be a cockpit for your verification environment. It ties to CVS
or Clearcase for configuration control, LSF or SGE for load management, and NC, VCS or Modelsim
for simulation.
Tanner sells a tool for managing verification that they say is independent of the verification
environment. It tracks progress and all current jobs. It is tied to CVS, Subversion, Clearcase and
Perforce, LSF and SGE, and VCS, Modelsim and NC-Sim.
Test tools
DAFCA is a new startup that sells wrappers for testing IP. They say their wrappers enable real-time
access of internal signals, at-speed observability and debug. The wrappers can use any of several
interface formats including P1500. The company had no booth, only a demo suite, but they were very
popular.
Magma has a full suite of their own test tools, including scan insertion, memory BIST, logic BIST with
test point insertion, as well as TAP and boundary scan insertion. The memory BIST has built-in hard or
soft repair capability and can share memory test controllers when there are a large number of
memories. It supports “physically aware DFT”. The tool detects if two lines are routed close together
for a long distance and will first try to space them apart. If that is not possible, the two nets are passed
on to the ATPG software and a pattern is created to test for bridging between the lines.
Mentor has a full suite of test tools including ATPG, scan insertion, memory and logic BIST and pattern
compression, and they are in the reference flow for TSMC. Their test tools are linked to Calibre so
they can take failure data from the test and try to identify the source in the GDSII database.
Syntest also has a full suite of test tools. They emphasize logic BIST combined with scan testing. They
propose using both for manufacturing testing and the BIST only for field-testing. This recommendation
is based on the fact that BIST alone would have lower coverage but require much less test hardware.
Syntest continues to be a great looking girl with no date for the prom; Cadence went off and got their
own test suite, and now Magma has done the same.
Logicvision emphasized the easy-to-use RTL integration of their BIST controllers. Because it’s done at
RTL there are no timing surprises. Their logic BIST architecture now allows for a “burst mode” that
permits true at-speed testing with the native clock for the circuitry.
Intellitech sells tools to support JTAG and boundary scan. They have an environment for debugging
chips once on a board that they claim can reduce debug time by 10X or more. It ties into Tetramax,
allowing one to scan out data around the failure to compare simulation data to actual results. Their
debugger is accessible over the network so it can be used from one’s desk. They also have a single
piece of IP that can both do embedded test and configure FPGAs in your system.
Genesys sells a tool for inserting BIST for memories such that dynamic soft repair is possible. They
have another fairly new tool which allows one to do ATPG on blocks, then put boundary scan around
the blocks and use this for the top level test. They say it makes for smaller, simpler vectors and is
cheaper than test compression tools.
DeFacTo Technologies sells a tool for RTL level scan insertion. Because scan exists in the RTL one
can verify scan chains without doing gate level simulation. I don’t know how this would work with the
inevitable scan chain reordering that occurs after placement.
Physical Synthesis
Anecdotally, Magma’s tools sound like they are killing Synopsys and Cadence tools in evaluations. If
they survive the lawsuit they will probably be a force to be reckoned with.
Synopsys IC Compiler sounds like their answer to Magma. The tool replaces Jupiter, Astro, Physical
Compiler and Primetime. It uses a unified data model and promises to do synthesis, placement, clock
tree synthesis and routing simultaneously. The input is a gate level netlist. During optimization, timing
analysis is done at all “critical” corners, and then for final closure it uses all corners. It also does timing
driven metal fill. It measures “critical area” – the total area where a particle could cause a failure, and
tries to minimize it. The tool will spread wires by half a pitch to improve yield. The interface is Tcl only.
Sierra Pinnacle is apparently some ex Synopsys folks who have created a physical synthesis tool. It
goes from gates to placed gates. The tool optimizes concurrently over multiple modes and corners and
can do up to 10 million gates flat overnight. They claim 2X to 3X better memory utilization and speed
than competitors but their key selling point is design for variability.
Static Timing Analysis
Probably the biggest news in this area is the tools that generate or check timing constraints.
Fishtail Design Automation sells a formal tool that pushes constraints down in a design and can
analyze and generate false and multi-cycle paths. Their tool also maps RTL level exceptions to the
netlist, including name changes, etc. They say they have done 5M gates flat and 10M hierarchically.
Their tool generally creates far more constraints than users might on their own because it is more
specific (they do source-destination pairs and often use “through” constructs) to avoid accidentally
listing something as a false path that really isn’t. For gate level verification it takes SDC and drives
Primetime.
Cadence now has a tool (from the old Verplex folks) that checks false paths as well as doing sort of
like a lint check on constraints. Coming soon are the ability to generate false path constraints and the
ability to generate and check multi-cycle path constraints.
Blue Pearl sells an RTL analysis tool for timing constraint generation and validation (false and multi-
cycle paths). The generation capability is apparently still in beta and there are no benchmarks yet.
The validation capability can be handy for IP that you have since modified.
Averant sells a tool that verifies false paths and multi-cycle paths. It does not generate constraints; it
just checks your SDC.
Real Intent is working on a tool to check timing exceptions. They currently just do verification; they are
planning to generate tools for false paths and multi-cycle paths next year.
Incentia sells a static timing analyzer that they say accepts Primetime scripts as-is. It can support
Signal Integrity and timing ECOs. Most customers are in Asia, and include NEC, Toshiba and Cisco.
SynApps has a static timing analyzer that they say is 20% faster than Primetime. It has aliases to take
all Primetime commands. Currently their synthesis and STA tools together cost only $5K/mo. They
have users in Japan, England and the US.
Avertec sells a tool for transistor level timing and signal integrity analysis. They also produce a .lib
model for IP that will have accurate timing. They claim this tool is much faster and has bigger capacity
than Pathmill. They report doing 1.6 M transistors and 12 M parasitics in a flat database in about 4
hours. They also have a tool that can create an HDL (VHDL or Verilog) view with timing from a SPICE
netlist – good for old IP (or reverse engineering). The tool that creates HDL does not need any
predefined library like Cadence/Verplex.
Golden Gate has a new tool that does 2.5 D extraction on power supply nets, including chips with
multiple supply voltages. Additionally it does static timing analysis and analyzes signal integrity.
Apache Design Solutions has a critical path signal integrity tool. It can take power supply drop and
crosstalk into consideration when analyzing critical timing.
Blade Technology sells a tool to do statistical timing of critical paths. There is an initial tool setup
where they quantify variability for each cell. In use, the input is a path from Primetime and the output is
a bell curve of possible delays of that path. They say results are super fast since Primetime has done
all the work.
Signal Integrity
Golden Gate has a new tool that does 2.5 D extraction on power supply nets, including chips with
multiple supply voltages, and can do static timing analysis and analyze signal integrity.
Optimal sells tools for analyzing signal and power integrity on PCBs, packages, bonding wires and I/O
buffers on chips. It does not do cables or connectors. Input is Cadence or Gerber data and SPICE
models.
Applied Simulation Technology sells an analysis tool for EMI, signal and power integrity of PCBs,
cables, and packages. They are now starting to apply it to ICs.
Sigrity sells tools for analyzing IR drop and signal integrity on boards and in packages. They say they
can do wire bonds and are now moving into full chip analysis.
IR Drop Analysis
Golden Gate has a new tool that does 2.5 D extraction on power supply nets, including chips with
multiple supply voltages, and can do static timing analysis and analyze signal integrity.
Synopsys has a new tool called Primerail which will be replacing Railmill. The use the same tables as
Nanosim but have a new engine. For transistor level simulation, it does an LVS on the layout, a
Nanosim simulation to get current waveforms, and then a Primerail analysis. For cell level analysis, it
does it’s own characterization of the cell library using HSPICE to get more detailed information than is
available in the .lib.
Power Tools
I attended a Cadence breakfast on power issues. The speakers from Cadence, Arm, Artisan, TSMC
and Applied Materials all presented product updates. The consensus of the speakers was that clients
perhaps are too concerned about timing versus power. They did an ARM processor in the normal flow
and then with a low power flow. The result was 40% lower power for a 90 nm design. Encounter now
automates Multiple Supply Voltage (MSV) design, which in this case meant a 1.0 V section and a 0.8 V
section. At 0.8 V, gates dissipate 36% less power. They defined a clock gating cell with Artisan and
85% of the registers wound up being gated. They noted that at 65 nm, about half the power is
leakage. In the test chip, about 90% of the gates in the 1.0 V section used high Vt cells, which
significantly reduced leakage. Interestingly, TSMC claimed that reductions in defect density are
accelerating at each technology node (i.e. they learn to improve yield faster with each new
technology). At the 90 nm node they have three technologies (high speed, general and low power)
and each of those has three threshold voltages available, resulting in quite a confusing mess if you
really want to optimize both speed and power.
ChipVision sells Orinoco, a tool that minimizes power at the architectural level. They claim that that is
the level with the greatest opportunity for power reduction. Their tool allows for tradeoffs like “what if I
unroll this loop”, etc. They claim 60-75% power savings and say their power estimates are within 25%
of the actual measured power.
Golden Gate sells a tool to minimize power using three methods: 1) capacitance rebalancing – it
reroutes signals so that the signals that switch most frequently have the least capacitance 2) wires first
– it keeps roughly the same placement but routes from the top levels down to minimize substrate
capacitance 3) clock optimization. They say these three schemes allow 10-25% reduction in power.
They prefer .lib files with signal integrity information but don’t yet support ECSM.
Apache has a tool for vectorless power estimation. They use SPICE on a library to get profiles of VDD
and VSS when cells are switching. They take this new library, plus your LEF/DEF, GDSII, packaging
model, and STA information (a window for each instance describing where within the cycle it might
switch). The result is a physically based estimate that includes on-chip and packaging parasitics. They
can also use VCD from the user or the tool can generate vectors automatically based on switching
activity levels. They sell another tool that does automatic power/ground busing, including suggestions
for decoupling capacitors.
Entasys sells a tool that does vectorless power estimation. The estimate is based on gate count, IO list
and LEF. They do some power constraints (like simultaneous switching constraints). They do
floorplanning for power and also vectorless power network verification.
BullDAST sells several tools for power analysis and optimization. They have an estimator that uses
libraries of large building blocks to estimate power based on RTL simulation. They can also modify the
clock structure, either adding gating to clocks based on lack of activity in RTL simulation, or combining
different gated clocks if simulation shows that they always turn on and off in unison.
Azuro sells a tool for reducing power in the clock tree. It is used after placement but before routing.
They claim a power reduction of up to 20%. They have reference flows for Cadence, Synopsys and
Magma.
Proficient Design sells two tools for reducing power. One does post-synthesis optimization, inserting
their own low power IP, and they claim this results in a 15-45% power reduction. The other optimizes
register files and FIFOs produced by Synopsys so they are smaller and use less power.
Prolific sells a tool to decrease power by swapping in lower power cells after routing.
Gradient Design Automation is working on tools for temperature variation across a chip. The input is
LEF/DEF or GDSII, output from a power tool, a description of the package (Gradient’s own format) and
technology information (their format). The output is temperature by instance and recommended
changes to the placement. They are working closely with Cadence. The analysis tool is shipping now
and the repair tool is in development but no release date is currently projected.
OEA sells three tools for power buses. One helps with planning, one crates the grid used by the logic
and one makes the ring for the I/O.
SPICE, etc.
Silvaco claims their SmartSPICE is the best selling tool in its class and is optimized for 64-bit operation.
Sandwork does no actual SPICE simulation but instead does SPICE linting, allows you to examine PWL
inputs before wasting time simulating them and then allows you to do some fancy analysis. Results can
be cut and pasted into Microsoft documents.
EverCAD sells a simulator that combines SPICE (they claim 2X-3X faster than HSPICE), a table-driven
SPICE-like simulator (they claim 2X-3X faster than HSIM) and a Verilog simulator, plus it ties into major
VHDL/Verilog simulator and Spectre.
Ansoft sells a simulator and design environment for RF design that links to Cadence Spectre. It
handles both time and frequency domain. They claim it is faster than HSPICE for large netlist.
FTL Systems says they are developing a hardware accelerator for analog simulation. They claim the
4U form factor box will have teraop processing power and will also be available for use as a
supercomputer.
Sigrity sells a tool to take S, Z or Y parameters and turns them into a SPICE circuit equivalent for
simulation.
SPICE-like simulators
The two biggest vendors used to be Synopsys (with the old Epic tools), and Nassda. Synopsys sued
Nassda (which was founded by ex-Synopsys people) for patent infringement and then bought them.
Interestingly Ellen Revelj of Intrinsix did a comparison several years ago and found them to be so
fundamentally different that it was nearly impossible to do an apples-to-apples comparison. They had
very different modes of operation and strengths and weaknesses; if the two sets of tools had a
common heritage they have both evolved quite a bit since then. Anyway, Synopsys said that current
plans are to retain both tools. Their current co-simulation environment includes VCS, HSPICE and
Nanosim, and they plan to integrate Nassda’s HSIM as well.
Mentor sells a new table driven simulator called MACH. Often in a mixed signal simulation there is
substantial setup of the digital portions before the system can do anything interesting in the analog
realm. This means you can burn a ton of CPU time simulating the analog portion during this long,
boring setup. Mentor’s simulator allows you to simulate the initialization of the digital portion in a digital-
only mode, and then switch over to a more accurate mode when something interesting starts to
happen on the analog side.
Nascentric sells a SPICE-like simulator that they say is current based (it does tunneling current, etc.).
They claim it is 10X faster than HSIM. It has no interfaces to other simulators.
EverCAD sells a simulator that combines SPICE (they claim 2X-3X faster than SPICE), a table-driven
SPICE-like simulator (they claim 2X-3X faster than HSIM) and a Verilog simulator, plus it ties into major
VHDL/Verilog simulator and Spectre.
Memories, Memory Compilers and Memory Models
Denali continues their dominance of all things memory. They sell their Databahn IP for interfaces to
serial ATA and SDR, DDR and now DDR2 running up to 400 MHz. Their Dataplex IP handles off chip
storage using interfaces like SATA, Flash and DDR. For verification IP, Denali sells a variety of
products to verify interfaces to memory and standard interfaces like serial ATA, PCI Express, and
Advanced Switching Interconnect. Their PureSpec tool now has API to hook to Verisity and Vera.
Virage says their nonvolatile memories are very popular for RF ID tags, security applications and
trimming. They now sell high density, high speed and low power versions of many RAMs. They will be
using Error Correcting Code on RAMS starting at 90 nm. Their standard memories have test
multiplexers and they sell their own BIST scheme. They emphasized that if you use their RAMS you
should also use their BIST. One of the key questions in BIST is how the logical addresses map to the
physical addresses. You want a cell to be surrounded by different values in the physically adjacent
cells, but it may not be clear what those cells are. In the Virage case it isn’t. Their mapping of logical to
physical addresses is encrypted so while other folks might be able to do simple checkerboards, they
can’t offer the ability to fully check a memory. Virage also emphasized their advantage that when using
a redundant column to repair a RAM, they de-power the bit lines to save power, which would not be
possible using a 3rd party scheme.
MoSys sells their patented 1 transistor SRAM, which they license to other vendors.
Silicon Design Solutions sells both compilers and custom instances allowing for embedded memories
including SRAMs, multi-port register files, CAMs and TLBs. Their compilers feature options for ultra-
low power, low leakage and full asynchronous operation.
Emerging Memory Technologies sells compilers for low leakage SRAM and DRAM memories. They
feature BIST repair that isolate weak bits to save power. Repair can be done using fuses of any type
the customer wants. They also support Error Correcting Code.
Interra Systems sells a tool that helps you create your own memory compilers, using their own custom
language.
Pulsic sells floorplanning as well as place and route software for custom designs like mixed signal or
RAMs (but not digital). They say their tool is used by 6 of the 10 largest RAM makers.
Legend Design Automation sells a memory characterization tool. It uses their own SPICE simulator that
they say has better speed and capacity than competitors. They also have a table driven SPICE-like
simulator.
Library Vendors
I’ve used at least two dozen libraries in my career and the next one I see without problems will be the
first one ever. The perhaps the more relevant question is how bad the errors are and where the errors
are located. I’ve also made libraries and library characterization software myself and mine were as
buggy as the commercial stuff. If you trust any library to be wholly correct you are naive.
Artisan has cleared out most of the competition using their model of providing free libraries, where the
foundry reimburses them when the design is fabricated.
Virage now uses a model of free libraries with some fabs, and charges for libraries when it does not
have an arrangement with the fab. They say they win a lot of business in the low power area.
Library Generation and Characterization
Nangate sells tools for customers to generate their own libraries. They have a running prototype and a
few customers in beta. They can create a range of libraries (fast, small, low Vt, etc.). They claim they
can do any library in 24 hours although I’ll be honest, that’s a *LOT* of SPICE simulation. They
currently use a two-dimensional (output load and slew rate) model and are working on current based
models.
Prolific does optimization for power, timing and signal integrity. It creates new cells with drive strengths
that are between the cells provided in your library. It combines cells of different drive strengths and
can also combine cells from various libraries (fast versus low power, for example) to create the optimal
specialized cell for your situation.
Z Circuit Automation sells a unique tool that compares libraries or cells within libraries. The tool works
from a .lib and can compare different revs of the same library as well as point out the best load/slew
ranges for a cell or a library, help set margins, etc. They have recently introduced a tool to do library
characterization as well. They claim that since it has been their job to find library bugs, they have the
most bug free characterization tool. You get a big discount if you buy their checker tool to check the
library they created.
FPGAs
Altera sells two main lines of FPGAs: the low cost Cyclone line and the high performance Stratix line.
The Cyclone line was designed for 90 nm specifically for cost reduction. One interesting set of devices
they have is their “Hardcopy” series. They will take an FPGA design and turn it into a “structured ASIC”
design, using two metal layers to customize their base array. They guarantee a successful transition
from the FPGA to the Hardcopy device. Because only two metal layers are customized, it minimized
mask NRE and they can provide parts in only 8 weeks. They claim logic is reduced up to 85% in size,
though memories and I/O stay the same size, resulting in up to a 90% cost reduction. They see this as
fitting in the middle of the life cycle. Initially customers might use a FPGA because they are not positive
the design is finalized and because they want to minimize time to market, then when production ramps
up they can go to the lower cost Hardcopy device, then when production tails off and becomes
uncertain they can burn FPGAs as needed for end-of-life production and for spare parts.
Synplicity has a new Amplify tool for physical synthesis of FPGAs in beta. It has new placement
algorithms that they claim result in better placement than Xilinx tools. Altera support is under
development. Their Identify tool allows you to debug an actual FPGA in an environment similar to a
simulator; you identify signals to probe, etc. in the RTL and it handles the details. Identify now handles
VHDL or Verilog. They said their Synplify ASIC tool, similar to CD Ultra, is selling quite well and ASIC
revenues account for 20-30% of the company’s income (remember, though the cost difference in tool
types). They have Designware equivalents. Their physical synthesis tool supports LSI, Fujitsu and
NEC. Synplicity sells a tool called Synplify DSP that accepts a MATLAB/Simulink description of your
algorithm plus some user inputs from a GUI and produces synthesizable RTL and a testbench. The
output RTL is customized for whatever FPGA you are targeting. This allows users to also target to an
ASIC but care needs to be taken to massage the result for RAM instantiations.
Mentor says their FPGA tools are improved due to the close coupling of both the physical and RTL
domains. They now allow cross probing of RTL to physical nets. They s also support very fast ECOs
without going back and forth in the tools. The cross probing is available for parts from Xilinx, Altera,
Actel and Lattice.
Structured/Platform ASICs
LSI Logic sells their Rapid Chip structured ASIC. They emphasize that they use fine grain architecture
as opposed to NEC so they claim better performance and density. Their devices can contain
memories, SERDS and PLLs. They use only 4 metal layers to save on NRE. They have no fixed clock
network so it can be customized to your needs. They have hard macros for processors (like ARM) that
have “landing zones” on their arrays, which will keep them close to cache memory, etc. Some arrays
have a big a big matrix of RAM that can be configured into any size and shape of RAM and includes
BIST logic. The designs are done using Synplicity Amplify.
VIASIC sells a via programmed structured ASIC. They provide the fabric and the software that maps a
Verilog netlist to it. They have Synopsys models for their cells made with various technologies (TSMC
0.13, IBM 0.13, Dungbu 0.13, etc.). The tool outputs SDF for post-route simulation. They utilize
separate logical (synthesis) and physical (delay annotation) library files. They have a limited variety of
physical cells yet a large variety of drive strengths by paralleling cells. Their tools route the clock
through the fabric that also contains RAM cells, with each bit of RAM occupying roughly the area of
one gate. Instead of having separate areas for RAM, the RAM and gate cells are intermixed to improve
routing because in some cases logic routing can go over the RAM cells.
Physical Design Planning
Tera Systems has pre-characterized libraries of large blocks (like adders and multipliers) that allow
them to quickly estimate size and speed of various design alternatives. New for this year is the ability
to optimize power and leakage. It also now does multi-Vt optimization and allows planning of voltage
islands. Their autoplacer can handle hundreds of macros.
Silicon Dimensions sells a design planning tool that checks SDC and helps do a quick floorplan. It
does a quick place and route to find mostly floorplanning issues. They didn’t like the term “virtual
physical prototyping” because they said that sounds like it’s aimed mostly at back-end designers, while
their tool is aimed at front-end folks and is priced in the range of a simulator.
Atrenta sells a tool called “1 team implement” with three pieces. One is for system architects and
partitions the RTL, comes up with timing and area budgets, etc. The second gives RTL coders access
to physical results without having to know how to do place and route. The third is a mixed hard macro
and standard cell floorplanner. The tool is built on OpenAccess and is fully native. The output is a
floorplan and placed gates. They do synthesis internally but recommend you use a real synthesis tool
for final results. BTW, Atrenta was just a linter company last year. They now employ 230 people and
apparently Synopsys is not pleased with their invasion of new turf.
Javelin Design Automation sells a tool that accepts full RTL, partial RTL or just black boxes plus
LEF/DEF while doing high level partitioning, congestion and timing analysis and outputting synthesis
constraints as well. Once synthesis is done, the tool takes the gate level netlist and does timing driven
placement. The tool outputs both block level and gate level PDEF or DEF.
Accelicon Technologies sells an analog virtual prototyping tool. The input is a Cadence Composer
schematic. It writes constraints and created a floorplan. The user can modify the constraints and do
what-if analysis to quickly examine alternative floorplans. The output is a Cadence database. They say
that for a 250-device design they can go from schematic to layout in 8 minutes.
Floorplanners
Synopsys said that the 2004.06 release is a very important one for Jupiter XT. It will include support or
multi-voltage power networks, non-uniform grids, automatic rings around blocks, shrinking a design
while maintaining the floorplan, and will support multi-instantiated modules. It also reduces total
negative slack to deal with on-chip variation.
Place and Route
Golden Gate sells a tool to minimize power using three methods: 1) capacitance rebalancing – it
reroutes signals so that the signals that switch most frequently have the least capacitance 2) wires first
– it keeps roughly the same placement but routes from the top levels down to minimize substrate
capacitance 3) clock optimization. They say these three schemes allow 10-25% reduction in power.
They prefer .lib files with signal integrity information but don’t yet support ECSM
ReShape sells a tool that reroutes designs (global routing with repeaters) to close timing and fix
congestion and signal integrity problems. They say most large designs can be completed overnight.
They currently are offering a free plasma TV if they can’t improve on your Cadence layout. They also
have an older tool that chops up a layout into pieces (which can be routed on different processors)
such that the pieces abut seamlessly, resulting in smaller area and a faster design.
Silicon Design Systems sells a tool that combines routing, extraction and static timing analysis. This
tool iterates routing (including resizing, topology changes and adding buffers) until timing and signal
integrity problems are solved. They say no manual intervention is needed, although you can do
progressive optimization and do hand tweaking at checkpoints. They say their STA engine is within 3-
5% of signoff tools.
Tera Route sells a shaped based router that they claim is faster than Cadence or Synopsys for large
designs. This is a router only (no placement) but they say it routes to completion.
Manhattan Routing sells a place and route debug tool that is intended to allow engineers to visualize
problems and generate ECOs without tying up expensive place and route licenses. It takes LEF/DEF, .
lib, etc. and timing reports and allows engineers to see the front end and back end at the same time. It
can retime the design based on SPEF and estimate routes if not routed yet. They have a separate tool
that helps with timing closure of that last few paths. Currently, their STA tool is within 3% of Primetime
which is obviously a problem. As a result this tool might say the problem is fixed while Primetime does
not. A full STA tool is in the works however no timeline is available.
Pulsic sells floorplanning and place and route software for custom designs like mixed signal or RAMs
(but not digital). They say their tool is used by 6 of the 10 largest RAM makers.
InternetCAD.com leases their entire suite of tools for $25K per year. For that you get a floor planner,
standard cell and gate array placer, and gridless global and detailed routers. Capacity is up to about
500K objects and most customers are doing mixed signal, etc.
OEA sells tools for design and analysis of clock networks and also bus structures.
Custom Layout
Cadence Virtuoso is probably still the dominant force in this market.
Silicon Canvas sells Laker, which they claim is superior to Cadence Virtuoso in many ways. They
report faster stream in and stream out, faster viewing, a better short locator, and that their magic cells
are better than Cadence P-cells. They claim a 20% productivity increase that they say translates into
2X faster project schedule. One price buys all features, which is not a claim.
Tanner has a new schematic entry tool going into beta that they say should provide better analog
support. They say they have better cross-probing now and have a node highlighter for easier
debugging. Their DRCs can use Calibre or Dracula rules directly without conversion and they can
import Virtuoso setup files. They say their “T-cells” are better than Cadence “P-cells” because they
are written in C and hence easier to support.
Silvaco sells a set of tools for schematic capture, layout and DRC. They have their own DRC format
but can read Diva and Dracula decks. They claim the tool is very popular in Japan.
IC Editors sells a very inexpensive layout editor (about $6K I’m told). It is a layout editor with DRC and
LVS aimed an analog and smaller digital circuits. They claim super fast plotting and can handle up to a
few million transistors. DRC/LVS rules are in their own format.
MyCAD sells an inexpensive layout editor with DRC, ERC and LVS capability. They say they can
handle about 1 million transistors flat and larger designs hierarchically. Their DRCs use their own rule
format but they can read Dracula rules.
OEA sells three tools for power buses. One helps with planning, one crates the grid used by the logic
and one makes the ring for the I/O.
Design for Yield
The two big issues here are:
1. There is no standard for transmitting yield information from a foundry for someone trying to
improve their yield
2. This is the most sensitive information that foundries possess so they will demand some sort of
encryption
A number of tools would gladly accept foundry specific information and change the layout in keeping
with their utility. Currently there is no way universal method to do that and I’m not aware of anyone
working on a standard. For example, Synopsys IC Compiler measures “critical area” (the total area
where a particle could cause a failure) and tries to minimize it. They said they would gladly take more
exact, foundry specific information but can’t get any. Mentor is also working on some standard
encrypted format but currently has to let the user make guesses.
Mentor’s Calibre is a major player in the design for yield area and most other vendors were comparing
their tools to this. Their tool does full analysis and limited modification to improve yield.
Aprio’ sells DFM software to do the OPC and RET, simulate it and fix small areas. They claim it is
similar speed-wise to Calibre.
Nannor sells a tool that does fixes based on recommended rules. It can do things like redundant vias,
line end spacing changes, avoidance of stacked vias, and wire spreading. The user can also specify
new rules using the Tcl interface.
Ponte sells a tool that analyzes yield detractors. The input is GDSII or LEF/DEF plus fab information,
and the output is detailed yield information. It gives yield by layer, highlights worst yielding nets, etc.
They can characterize libraries and IP.
CommandCAD sells fast pattern matching software that looks for yield detractors that might still pass
DRC checks. They say they can spot areas where OPC will have problems. They emphasized that
their approach is 2D, unlike 1 dimensional DRC checks. They get yield information from the fab
(format??).
KLA has a tool called Design Scan that allows full chip process window simulation. The input is the
mask data after Optical Proximity Correction (OPC). They claim that in only 2-4 hours they can
simulate an 8mm by 8mm die over 35 focusing exposure conditions. They have an older tool called
Prolith that is aimed more at simulation of individual cells.
Sigma-C sells what they claim is the only tool to do 3D resist simulation. The depth of focus of modern
equipment is extremely small, so 3D simulation, which models how the resist is developed throughout
its height, can spot problems that normal 2D simulation can’t. The problem is that is it amazingly CPU
intensive. Currently their tool can only do a small portion of a cell. A new product due out 4Q05 should
be able to do an entire standard cell.
ChipMD sells tools that do Design for Yield (at a circuit level, not a mask level) for analog devices. One
does circuit optimization for yield using Monte Carlo simulation, and one does worst case analysis
without using Monte Carlo methods. Both create SPICE scripts for your own simulator (they don’t
provide a simulator).
Clear Shape Technologies is a DFM company that had no products out yet as of DAC.
Compactors/Expanders
These tools have always had a number of possible uses and it’s been interesting to see the evolution
of the sales pitch over the years as one reason for using them becomes obsolete but another
becomes reasonable. Currently the big motivators are design for manufacturing/yield and process
migration.
The Sagantec folks said they are getting lots of interest in their Design for Manufacturability stuff.
They say their customers have working silicon at 65 nanometers and their tools are being used on a
45 nanometer design. Their tool does things like doubling vias and increasing overlap around vias as
well as fixing DRC violations. They also have a tool called Anaconda for analog checking. The user
can specify properties on a schematic (like symmetry) and the tool checks for those properties.
Rubicad again did not attend DAC – I heard that at least last year they just didn’t think it was worth the
money.
Analog/RF Tools
Xpedion sells a frequency domain simulator tool called “Golden Gate” (not to be confused with the IR
drop analysis folks). They say is better than the tools from Agilent or the recent competing tool from
Cadence. Interestingly, Cadence is an investor in this company. They integrate into Cadence and take
a Cadence design kit from the foundry, and say most new customers are up in only one day. They are
proud of their support team, which they say is larger than those of the competitors combined. They are
also proud of the capacity of the tool, which they say can do an entire radio chain at the transistor
level with parasitics. They have a new browser that allows users to preview waveforms without tying up
a simulator license. It allows the user to copy the waveform to a clipboard, save the image for use in
Microsoft docs, or email the waveform in an ASCII format.
Agilent says their frequency domain simulator has better capacity and performance than their
competitors, and says they’ve done designs as large at 17K transistors. They are now moving into
simulation of PLLs for jitter, etc. and are integrating their EM tools into the Cadence environment.
Sagantec has a tool called Anaconda for analog checking. The user can specify properties on a
schematic (like symmetry) and the tool checks for those properties.
Mentor sells a set of tools (schematic capture, simulation and layout) for analog/RF design and says
their edge is in mixing analog and RF in simulation of a large system.
Applied Wave Research sells several tools for analog and RF design. Most tools plug into a Cadence
environment. They can do schematic entry and simulation using both HSPICE and their own frequency
domain simulator. Their signal integrity design suite can simulate a PCB, package, bonding wire and
chip in a single simulation. They also have a high-level system design tool for communications systems
that can simulate things like bit error rates.
Ansoft sells an environment for RF design, including a simulator that operates in both time and
frequency domains. They also have two tools for EM/signal integrity analysis. One is a full 3D tool that
has the necessary accuracy for cables, wire bonds, connectors, etc. and the other is a 2.5D tool that
is faster and good for packages and PCBs.
Anasift Technology sells a tool for analog optimization. The input is a netlist and the output is a sized
netlist. They have their own simulation engine, which they claim is within 0.1% of HSPICE. Their tool
can do symbolic analysis; extract a transfer function and does unlimited corners and parameters. They
claim that, unlike many competing tools, their tool needs no good starting point to do an optimization.
They typically run optimization with a small number of corners, then verify with all corners. If it fails,
they optimize again using the corners that failed. In one benchmark, they did 3 op amps. These had
taken 4 weeks to do prior. With their tool it took 1 day, saving a total of 10 man weeks.
Orora sells two analog/RF tools. The first takes a design, expressed in a Cadence schematic or SPICE
netlist, and then derives equations for it, allowing analysis of poles and zeros, sensitivity, etc. The
second selects a topology from ones you provided, optimizes the design and does a yield analysis
(“analog synthesis” – netlist to sized netlist). They use whatever simulator you have and can support
multiprocessing.
Berkeley Design sells a tool for analysis of Phase Locked Loops. It analyzed phase noise and does
jitter design. They say it has been used on 35 designs in 12 different processes.
ChipMD sells tools that do Design for Yield (at a circuit level, not a mask level) for analog devices. One
does circuit optimization for yield using Monte Carlo simulation, and one does worst case analysis
without using Monte Carlo methods. Both create SPICE scripts for your own simulator (they don’t
provide a simulator).
OEA sells tools for RF component analysis, inductor design and 3D inductor analysis.
Lorentz Solutions sells tools to create passive components. Their tools support EM design and
verification, and support EM coupling. They claim their tools are faster than the competition, and say
they can design an inductor in 1-2 minutes.
Triad Semiconductor sells a mixed signal structured ASIC that is customized with only one mask layer.
They feel their sweet spot is from around 5K to 100K parts.
Accelicon Technologies sells an analog virtual prototyping tool. The input is a Cadence Composer
schematic. It writes constraints and created a floorplan. The user can modify the constraints and do
what-if analysis to quickly examine alternative floorplans. The output is a Cadence database. They say
that for a 250 device design they can go from schematic to layout in 8 minutes.
DRC, ERC, LVS
Mentor Calibre currently dominates this market. It no does RCL extraction, including self inductance
and mutual inductance. Calibre ADP (Advanced Device Parametrics) now supports in-die variation. It
handles metal fill capacitance as well, and is also integrated to Advance MS (Mixed Signal) so it can do
SPF for digital portions of your circuit and various formats for the analog portions. It integrates into the
Cadence schematic environment.
Magma says their new Mohave tool, which can run on multiple machines (not just multiple processors)
is 40X-50X faster than Calibre.
Parasitic Extraction
EDXACT sells an interesting tool for parasitic reduction. Extraction tools create very accurate, detailed
files that are too large to use and are then reduced (DSPF becomes RSPF). They create a file that is
somewhere in the middle between what people normally use; it is a bit larger but they claim much more
accurate than what people normally use to get actual timing. They say they are the only vendor who
properly handles coupling capacitance.
Optem Engineering sells 2D and true 3D extraction tools, including one for cables (which is extremely
rare). New for this year is a new model for silicon. They use an extra accurate model for the first few
microns below the surface, which they say allows for better modeling of oscillators.
Silvaco sells a variety of 2D and 3D field solvers for full chips, inductors or custom cells.
OEA sells tools for 3D analysis of critical nets, and for extraction of SPICE models of cells and blocks.
Mask Related Tools
Xyalis sells a metal fill tool that is rule based (can use any shape) resulting in a much smaller database
than their competitors according to their data.
Shearwater sells Lavis, a Japanese tool that is a viewer for GDSII, LEF/DEF, MEBES, etc. but also
allows editing and Boolean operations. They claim is high performance and high capacity and is used
by Aprio for their viewer. They sell another tool from Saratoga Data that optimizes and compresses
GDSII data. They say compression is 75%-98% and averages about 96%, while still retaining hierarchy.
Artwork Conversion Software sells a variety of utilities such as fast GDSII and MEBES viewers and
plotters, and tools that can do Boolean operations on GDSII or extract pad information automatically.
Laflin sells Hotscope, a high speed GDSII and MEBES viewer.
Brion Technologies sells a mask inspection tool that they say is faster than KLA because they have a
hardware accelerator.
Board Tools
EMA Design Automation sells both the venerable ORCAD tools and the Cadence Allegro tools – quite
a cadre of design entry and simulation choices.
Optimal Corp. sells tools for analyzing signal and power integrity on PCBs, packages, bonding wires
and I/O buffers on chips. It does not do cables or connectors. Input is Cadence or Gerber data and
SPICE models.
Sigrity sells tools for analyzing IR drop and signal integrity on boards and in packages.
Dynamic Details, Inc. sells bard circuit boards, and emphasized they can do quick prototypes from 2 to
44 layers. They do basically everything except ceramic and flex boards.
Design Collaboration, Configuration Control & Similar Tools
Synchronicity sells tools for design collaboration and version management. Matrix One, who makes
more traditional business software, recently acquired this firm. They have now integrated the two
together, so that if your design fails DRC the project manager now knows exactly what this means on
his Gantt charts.
ClioSoft has a design management and collaboration tool that originally was aimed at Cadence users,
but now supports Mentor as well. They say one could also use it with Synopsys or Magma but the
degree of integration into the native database is not as great.
IC Manage sells EDA design management software like Synchronicity or ClioSoft. It is built on Perforce.
It features revision control, configuration management, and multi-site collaboration, and cross-coupled
defect tracking. Perforce does a single connection for all files so they say it is much faster than
competitors, and if it is interrupted files are not out-of-sync; either all files are updated or none are.
They claim a Cadence benchmark showed them to be clearly superior. Licenses run about $1800 per
seat depending on quantity.
ReShape sells a tool called PD Builder that helps enforce a user defined design flow, and used
Perforce for version control. They say it helps with collaboration and also introduces the idea of
“design flow IP”.
Runtime Design Automation sells a workflow management tool. They say it is good for large teams with
a mix of experienced and inexperienced people. They say it can actually detect dependencies on the
fly.
EMA Design Automation sells a tool aimed at configuration control of PCBs.
Other
Silvaco, which sells a number of related tools in the TCAD, analog and to a lesser extent digital realm,
has a new license model for small companies. It’s called an “omnilicense” and it allows someone to run
any one tool at a time.
LSF-Macrovision, who make the highly popular FlexLM licensing tool, and are releasing a new tool to
monitor license usage and help you justify the licenses you own or want to buy.
Open iT sells software for monitoring license usage that they say it more accurate than the tool from
Macrovision, which they say overestimates usage. Theirs can report active versus inactive license
usage based on keystrokes, mouse clicks, etc. Based on how it is set up, it can warn users that they
have a license they have not been using for some period of time, and after some other programmable
period of time it will suspend the job and take back the license. Then the user comes back on Monday
morning there will be a popup that allows them to get the license back. For 35 users the tool is about
$140 per user plus a $10,000 setup fee.
Runtime Design Automation sells workload management tools that they say are better tuned to the
needs of EDA. They point out that unlike typical payroll jobs, a much larger portion of EDA jobs fail,
and different EDA jobs can take radically different periods of time. For the really fast jobs, scheduling
needs to be done quickly to maximize use of licenses.
Athena Design sells software to chop up large jobs and run them on different machines not simply on
different processors on the same machines. This can be done either under user control or it can be
automatically partitioned using an algorithm. Typical uses are static timing analysis, extraction (each
processor would get a piece of the design) and ECO routing. The algorithmic control requires them to
code up the algorithm; so far they’ve done extraction and incremental routing.
Avery Design Systems sells a tool to partition the digital simulation task among different processors
(this is not one of the easier tasks to split up).
Xoomsys sells a tool to partition SPICE simulations so that multiple processors can be used.
Handshake Solutions sells some interesting technology for asynchronous (no clock) logic. I didn’t get
details this year but last year they said the input is something like behavioral Verilog and their output is
a Verilog netlist for certain vendors which uses a “done” signal to start the next operation. They were
selling this for power but also the lack of a clock can mean one less pin in circuits that are primarily
analog but have some digital content. This type of design also has fewer EM/supply drop issues since
power is drawn more uniformly, rather than as a huge slug whenever the clock changes.
Prolific sells a tool to improve timing by swapping cells after routing.
Zenasis sells tools that create new cells to speed your critical path in a COT flow. They identify groups
of cells in your critical path and create a single new cell, which may involve reducing the number of
logic levels, sizing transistors, etc. The tools interact with Cadabra and Calibre to create layouts for the
new cluster cell. They claim a 10% to 15% speed increase. Their tools work with Synopsys, Cadence
and Magma; foundries they support include TSMC and UMC.
OEA sells three tools for power buses. One helps with planning, one creates the grid used by the logic
and one makes the ring for the I/O. They also have a tool for optimizing clock networks and another for
optimizing bus routing.
EMA Design Automation sells a tool that makes “intelligent timing diagrams”. The database
understands the relationships between signals and they say can prevent many errors in drawing new
diagrams.
Critical Blue sells software to automate the job of creating a coprocessor. First you profile your code
running on an ARM and identify commonly used functions. Add cycle times and constraints and the
tool creates a coprocessor for your ARM.
Target Compiler sells a suite for developing compilers etc. for new processors. The processor must be
described in their own language. It creates the compiler, linker etc. plus the HDL ISS simulator and
debugger, plus a test program for the processor. They say they also support ASIPs better than their
competition and allow highly parallel architectures.
Avertec has a tool that can create an RTL view with timing from a SPICE netlist – good for old IP (or
reverse engineering).
The Korean government paid for a booth for four vendors, who did IP, and AMBA development kit, an
MP3 chip and IP and database management. Their English sure beat my Korean but I still had a hard
time getting details.
Shearwater is representing a tool called Flume, currently in pre-release, which optimizes transfer of
large files. It has built-in Error Correcting Code.
Several vendors made tools for people who make tools. Their products could be very useful if you
have an internal EDA group developing tools that don’t want to reinvent the wheel.
• Verific Design Automation sells VHDL, Verilog and System Verilog parsers, analyzers and
elaborators.
• Interra also sells a variety of building blocks like VHDL and Verilog parsers and also markets an
unusual tool to create memory generators.
• Quintics sells a schematic generation tool that integrates into Virtuoso and they will make API to
integrate it into other tools at a cost of about $2K per seat.
• Concept Engineering also sells a schematic generation tool.
• Softjin is a Bangalore based company that creates EDA for other users, and has a number of
readers and writers for standard formats and for their own database.
• Silicon Navigator sells a framework built on OpenAccess and say Lucent is a customer.
• Praesagus sells a tool to model the variation in copper thickness due to CMP (Chemical
Mechanical Polishing - that’s why metal fill is added).
Parties
Best Party: Denali’s party, which was again at the House of Blues. It featured various industry bigwigs
playinthe blues and John Cooley in a chicken suit (he lost a bet).
Best giveaway: I was lucky enough to win a 50” TV from Altera so I’ll have to go with that. Aprio’s giant
inflated hammer that made a squeaky noise when you hit anything was also a hit. SoftJin gave away
very nice leather wallets.
Best booth show: the guy at Calypto who escaped from a straightjacket while riding a 6-foot high
unicycle. Scary stuff.